Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning

YE Juyang; CHEN Qilin; WANG Yaohua

doi:10.11999/JEIT260645

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YE Juyang, CHEN Qilin, WANG Yaohua. Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260645

Citation:

YE Juyang, CHEN Qilin, WANG Yaohua. Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260645

YE Juyang, CHEN Qilin, WANG Yaohua. Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260645

Citation:

YE Juyang, CHEN Qilin, WANG Yaohua. Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260645

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Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning

doi: 10.11999/JEIT260645 cstr: 32379.14.JEIT260645

College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China

Accepted Date: 2026-08-10
Rev Recd Date: 2026-08-10

Available Online: 2026-08-12

Abstract

Abstract

Objective One of the core challenges in applying machine learning techniques to electronic design automation (EDA) lies in learning high-quality circuit representations from large-scale gate-level netlists. As modern digital integrated circuits scale to tens of millions of gates, existing methods based on graph neural networks (GNNs) and graph transformers (GTs) suffer from excessive computational and memory overhead, rendering them impractical for industrial-scale designs. The fundamental issue is the lack of a proper tokenization mechanism for netlists—unlike natural language, where subword tokenization effectively compresses long sequences, the circuit domain lacks an analogous decomposition strategy that preserves functional semantics while reducing the effective graph size. This work aims to bridge this gap by introducing a hypergraph-partitioning-based circuit tokenizer that decomposes massive netlists into functionally cohesive sub-circuits, termed circuit elements, thereby enabling scalable and fine-grained representation learning. Methods This paper proposes a function-aware hypergraph partitioning driven framework for large-scale circuit representation learning. Inspired by the tokenization paradigm of large language models, the framework first models a gate-level netlist as a directed hypergraph, where gates are nodes and signals are hyperedges that can connect multiple gates. A novel optimization objective, the Functional Independence Ratio (FIR), is introduced to guide the partitioning process. FIR incorporates circuit structural priors and a bus recognition correction mechanism that identifies bus-structured signals based on structural similarity (gate type purity across predecessor/successor levels) and spatial similarity (topological distance variance within candidate groups). The bus recognition module corrects the effective interface count, ensuring that functionally cohesive modules are not penalized for using wide buses. An iterative greedy refinement procedure accepts only moves that strictly decrease FIR, converging to a locally optimal partition. On top of the partitioned circuit elements, a two-stage self-supervised pretraining framework is designed. In the first stage, a masked autoencoder with edge prediction tasks is applied to the coarse-grained circuit-element graph, learning global inter-element dependencies. The graph transformer encoder is then frozen and circuit element embeddings are saved. In the second stage, within each circuit element, a contrastive learning scheme is employed at the gate level. Positive pairs are constructed via Boolean equivalence transformations (e.g., associativity, De Morgan's laws), which preserve the Boolean function while altering the gate-level structure. Negative pairs are drawn from functionally different circuit elements within the same batch. The training jointly optimizes node-level and local-global alignment losses. A feature-wise modulation mechanism injects circuit-element-level context into gate-level representations, enabling the same gate type to acquire different embeddings depending on its functional context. Results and Discussions Extensive experiments are conducted on circuits collected from multiple sources, including ITC99, EPFL, OpenCores, and three RISC-V SoC designs (Rocket, BOOM, and OpenC910), with the largest design containing 22.3 million gates. For the tokenizer evaluation, FIR-based partitioning is compared against Mt-kahypar using the Adjusted Mutual Information (AMI) and Adjusted Rand Index (ARI) metrics, with the original module hierarchy serving as ground truth. Across all three RISC-V designs, FIR achieves AMI improvements of 24.6% to 27.1% and ARI improvements of 25.5% to 35.8% over Mt-kahypar, demonstrating consistent and substantial gains in functional coherence. On downstream tasks, the proposed method consistently outperforms state-of-the-art baselines including DeepGate4 and NetTAG across all comparable datasets. For full-circuit function recognition, the proposed method achieves F1 scores of 0.896, 0.861, 0.817, and 0.773 on ITC99, EPFL, OpenCores, and Rocket, respectively, representing improvements of 10.0% to 15.4% over the strongest baseline. Crucially, on BOOM (8.12M gates) and OpenC910 (22.3M gates), the proposed method is the only approach capable of completing training without running out of memory, achieving F1 scores of 0.771 and 0.748 for full-circuit tasks and 0.723 and 0.679 for gate-level tasks, respectively. Ablation studies with six model variants reveal a clear division of labor: the module-level pretraining stage dominates full-circuit performance (20.9% F1 drop when removed), while the gate-level pretraining stage dominates gate-level performance (26.1% F1 drop when removed). The FIR partitioning objective contributes 8.6% and 11.7% F1 improvements at the full-circuit and gate levels, respectively. The bus recognition module and the two-stage architecture also show consistent positive contributions across all metrics. Conclusions This paper presents a novel framework that addresses the scalability challenge in circuit representation learning by introducing a function-aware hypergraph partitioning tokenizer and a two-stage self-supervised pretraining architecture. The key insight is that by abstracting the intermediate circuit element level between individual gates and the full circuit, one can achieve both scalability to multi-million-gate designs and fine-grained gate-level discriminative capability. The proposed FIR objective effectively captures functional cohesion during partitioning, and the two-stage pretraining framework decouples global context learning from local representation refinement. Experimental results demonstrate state-of-the-art performance on function recognition tasks and, more importantly, the unique ability to scale to industrial-sized designs where existing methods fail. Future work includes extending the framework to other EDA tasks such as logic synthesis and physical design, exploring more aggressive hierarchical strategies for billion-gate designs, and adapting the bus recognition mechanism to non-standard cell libraries.
- Circuit Representation Learning,
- Hypergraph Partitioning,
- Self-Supervised Pretraining,
- Graph Transformer

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References(33)

References

[1]	HUANG Guyue, HU Jingbo, HE Yifan, et al. Machine learning for electronic design automation: A survey[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2021, 26(5): 40. doi: 10.1145/3451179.
[2]	SHI Zhengyuan, ZHENG Ziyang, KHAN S, et al. DeepGate3: Towards scalable circuit representation learning[C]. Proceedings of 2024 ACM/IEEE International Conference on Computer Aided Design, Newark, USA, 2024: 1–9. doi: 10.1145/3676536.3676791.
[3]	WANG Ziyi, BAI Chen, HE Zhuolun, et al. FGNN2: A powerful pretraining framework for learning the logic functionality of circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, 44(1): 227–240. doi: 10.1109/TCAD.2024.3434464.
[4]	CHEN Lei, CHEN Yiqi, CHU Zhufei, et al. Large circuit models: Opportunities and challenges[J]. Science China Information Sciences, 2024, 67(10): 200402. doi: 10.1007/s11432-024-4155-7.
[5]	ZHENG Ziyang, HUANG Shan, ZHONG Jianyuan, et al. DeepGate4: Efficient and effective representation learning for circuit design at scale[C]. Proceedings of the 13th International Conference on Learning Representations, Singapore, Singapore, 2025: 20972–20990.
[6]	FANG Wenji, LI Wenkai, LIU Shang, et al. NetTAG: A multimodal RTL-and-layout-aligned netlist foundation model via text-attributed graph[C]. Proceedings of the 62nd ACM/IEEE Design Automation Conference, San Francisco, USA, 2025: 1–7. doi: 10.1109/DAC63849.2025.11133349.
[7]	VASWANI A, SHAZEER N, PARMAR N, et al. Attention is all you need[C]. Proceedings of the 31st International Conference on Neural Information Processing Systems, Long Beach, USA, 2017: 6000–6010.
[8]	孙林慧, 成乐洋, 杨欣悦, 等. 基于Mamba上下文感知细粒度融合的多模态情感识别[J]. 电子与信息学报, 2026, 48(5): 1948–1959. doi: 10.11999/JEIT251307. SUN Linhui, CHENG Leyang, YANG Xinyue, et al. Context-aware fine-grained multimodal emotion recognition based on Mamba[J]. Journal of Electronics & Information Technology, 2026, 48(5): 1948–1959. doi: 10.11999/JEIT251307.
[9]	YING Chengxuan, CAI Tianle, LUO Shengjie, et al. Do transformers really perform bad for graph representation?[C]. Proceedings of the 35th International Conference on Neural Information Processing Systems, 2021: 2212. (查阅网上资料, 未找到对应的出版地信息, 请确认).
[10]	SUN Hao, SHEN Junzhong, ZHANG Tian, et al. FAMS: A framework of memory-centric mapping for DNNs on systolic array accelerators[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025, 33(4): 976–989. doi: 10.1109/TVLSI.2024.3522326.
[11]	李天阳, 张帆, 王松, 等. 基于FPGA的卷积神经网络和视觉Transformer通用加速器[J]. 电子与信息学报, 2024, 46(6): 2663–2672. doi: 10.11999/JEIT230713. LI Tianyang, ZHANG Fan, WANG Song, et al. FPGA-based unified accelerator for convolutional neural network and vision Transformer[J]. Journal of Electronics & Information Technology, 2024, 46(6): 2663–2672. doi: 10.11999/JEIT230713.
[12]	SENNRICH R, HADDOW B, and BIRCH A. Neural machine translation of rare words with subword units[C]. Proceedings of the 54th Annual Meeting of the Association for Computational Linguistics, Berlin, Germany, 2016: 1715–1725. doi: 10.18653/v1/P16-1162.
[13]	王泽昊, 朱振华, 谢童欣, 等. 混合专家大语言模型的系统与架构优化技术综述[J]. 电子与信息学报, 2025, 47(11): 4055–4078. doi: 10.11999/JEIT250407. WANG Zehao, ZHU Zhenhua, XIE Tongxin, et al. A survey on system and architecture optimization techniques for mixture-of-experts large language models[J]. Journal of Electronics & Information Technology, 2025, 47(11): 4055–4078. doi: 10.11999/JEIT250407.
[14]	FIDUCCIA C M and MATTHEYSES R M. A linear-time heuristic for improving network partitions[C]. Proceedings of the 19th Design Automation Conference, Las Vegas, USA, 1982: 175–181. doi: 10.1109/DAC.1982.1585498.
[15]	KARYPIS G, AGGARWAL R, KUMAR V, et al. Multilevel hypergraph partitioning: Application in VLSI domain[C]. Proceedings of the 34th Annual Design Automation Conference, Anaheim, USA, 1997: 526–529. doi: 10.1145/266021.266273.
[16]	AKHREMTSEV Y, HEUER T, SANDERS P, et al. Engineering a direct k-way hypergraph partitioning algorithm[C]. Proceedings of the 19th Workshop on Algorithm Engineering and Experiments, Barcelona, Spain, 2017: 28–42.
[17]	GOTTESBÜREN L, HEUER T, MAAS N, et al. Scalable high-quality hypergraph partitioning[J]. ACM Transactions on Algorithms, 2024, 20(1): 9. doi: 10.1145/3626527.
[18]	DAVIDSON S. ITC'99 benchmark circuits - preliminary results[C]. Proceedings of the International Test Conference 1999, Atlantic City, USA, 1999: 1125–1125. doi: 10.1109/TEST.1999.805857.
[19]	AMARÚ L, GAILLARDON P E, and DE MICHELI G. The EPFL combinational benchmark suite[C]. Proceedings of the 24th International Workshop on Logic & Synthesis, 2015. (查阅网上资料, 未找到对应的出版地信息, 请确认).
[20]	OPENCORES. The reference community for free and open source gateware IP cores[EB/OL]. https://opencores.org/, 2026. (查阅网上资料,请核对网址与文献是否相符).
[21]	ASANOVIĆ K, AVIZIENIS R, BACHRACH J, et al. The rocket chip generator[R]. Technical Report No. UCB/EECS-2016-17, 2016.
[22]	ZHAO J, KORPAN B, GONZALEZ A, et al. SonicBOOM: The 3rd generation Berkeley out-of-order machine[C]. Proceedings of the Fourth Workshop on Computer Architecture Research with RISC-V, Valencia, Spain, 2020: 1–7. (查阅网上资料, 未找到对应的出版地信息, 请确认).
[23]	CHEN Chen, XIANG Xiaoyan, LIU Chang, et al. Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension[C]. Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture, Valencia, Spain, 2020: 52–64. doi: 10.1109/ISCA45697.2020.00016.
[24]	PAN Jingyu, ZHOU Guanglei, CHANG C C, et al. A survey of research in large language models for electronic design automation[J]. ACM Transactions on Design Automation of Electronic Systems, 2025, 30(3): 34. doi: 10.1145/3715324.
[25]	ABDOLLAHI M, YEGANLI S F, BAHARLOO M, et al. Hardware design and verification with large language models: A scoping review, challenges, and open issues[J]. Electronics, 2024, 14(1): 120. doi: 10.3390/electronics14010120.
[26]	FANG Wenji, LIU Shang, WANG Jing, et al. CircuitFusion: Multimodal circuit representation learning for agile chip design[C]. Proceedings of the 13th International Conference on Learning Representations, Singapore, Singapore, 2025: 73554–73576.
[27]	WU Haoyuan, ZHENG Haisheng, PU Yuan, et al. Circuit representation learning with masked gate modeling and Verilog-AIG alignment[C]. Proceedings of the 13th International Conference on Learning Representations, Singapore, Singapore, 2025: 86691–86707.
[28]	GAI Jiahao, CHEN Hao, WANG Zhican, et al. Exploring code language models for automated HLS-based hardware generation: Benchmark, infrastructure and analysis[C]. Proceedings of the 30th Asia and South Pacific Design Automation Conference, Tokyo, Japan, 2025: 988–994. https://doi.org/10.1145/3658617.3697616.
[29]	SHIRZAD H, VELINGKER A, VENKATACHALAM B, et al. EXPHORMER: Sparse transformers for graphs[C]. Proceedings of the 40th International Conference on Machine Learning, Honolulu, USA, 2023: 1310.
[30]	WOLF C, GLASER J, and KEPLER J. Yosys - a free Verilog synthesis suite[C]. Proceedings of the 21st Austrian Workshop on Microelectronics, Linz, Austria, 2013: 1–6.
[31]	VINH N X, EPPS J, and BAILEY J. Information theoretic measures for clusterings comparison: Is a correction for chance necessary?[C]. Proceedings of the 26th Annual International Conference on Machine Learning, Montreal, Canada, 2009: 1073–1080. doi: 10.1145/1553374.1553511.
[32]	HUBERT L and ARABIE P. Comparing partitions[J]. Journal of Classification, 1985, 2(1): 193–218. doi: 10.1007/BF01908075.
[33]	周康, 侯波, 王力纬, 等. 融合CNN-LSTM的硬件木马旁路检测方法[J]. 电子与信息学报, 2025, 47(9): 3312–3320. doi: 10.11999/JEIT250241. ZHOU Kang, HOU Bo, WANG Liwei, et al. A CNN-LSTM fusion-based method for detecting hardware Trojan bypasses[J]. Journal of Electronics & Information Technology, 2025, 47(9): 3312–3320. doi: 10.11999/JEIT250241.