Point-Wise Single-Gate Recurrent Unit for Edge Temporal Inference and Its Memristor-Based In-Memory Computing Circuit Implementation

QI Haoming; HAN Juntao; PU Xiangrong; LI Zihao; ZHANG Zhang

doi:10.11999/JEIT260630

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QI Haoming, HAN Juntao, PU Xiangrong, LI Zihao, ZHANG Zhang. Point-Wise Single-Gate Recurrent Unit for Edge Temporal Inference and Its Memristor-Based In-Memory Computing Circuit Implementation[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260630

Citation:

QI Haoming, HAN Juntao, PU Xiangrong, LI Zihao, ZHANG Zhang. Point-Wise Single-Gate Recurrent Unit for Edge Temporal Inference and Its Memristor-Based In-Memory Computing Circuit Implementation[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260630

Citation:

QI Haoming, HAN Juntao, PU Xiangrong, LI Zihao, ZHANG Zhang. Point-Wise Single-Gate Recurrent Unit for Edge Temporal Inference and Its Memristor-Based In-Memory Computing Circuit Implementation[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260630

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Point-Wise Single-Gate Recurrent Unit for Edge Temporal Inference and Its Memristor-Based In-Memory Computing Circuit Implementation

doi: 10.11999/JEIT260630 cstr: 32379.14.JEIT260630

School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: Natural Science Foundation of Anhui Province (2308085MF207)

Received Date: 2026-05-15
Accepted Date: 2026-09-30
Rev Recd Date: 2026-07-24

Available Online: 2026-10-13

Abstract

Abstract

Objective With the rapid development of edge intelligence, wearable electronics, and Internet-of-Things applications, edge devices increasingly require low-latency and low-power temporal inference under limited storage and hardware resources. Gated recurrent neural networks, such as Long Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU), provide strong sequence modeling capability, but their dense hidden-to-hidden transformations introduce considerable parameter storage and vector-matrix multiplication overhead. In addition, the serial dependency between gate-related computation and candidate hidden-state computation increases the intra-step recurrent delay, which limits their efficient deployment in resource-constrained edge systems. Memristor-based in-memory computing can reduce data movement and accelerate vector-matrix operations, but directly mapping conventional gated recurrent structures onto memristor circuits still suffers from complex recurrent paths and peripheral circuit overhead. Therefore, a recurrent structure that jointly considers lightweight recurrence, intra-step parallelism, and hardware implementation efficiency is needed. To address this issue, this paper proposes a Point-Wise Single-Gate Recurrent Unit (P-SGRU) and a corresponding memristor-based in-memory computing circuit for efficient edge temporal inference.Methods P-SGRU is designed to simplify the recurrent path of conventional gated recurrent units. It replaces the fully connected hidden-to-hidden transformation with point-wise recurrent modulation, so that each hidden-state channel is recurrently modulated only by its corresponding channel at the previous time step. A single retention coefficient is introduced to control the fusion of the previous hidden state and the candidate hidden state. By removing the reset-gate-related dependency in GRU, the retention-coefficient branch and the candidate hidden-state branch can be computed in parallel within the same time step, thereby improving intra-step computational parallelism. According to the P-SGRU computation process, a memristor-based in-memory computing circuit is designed, consisting of a retention-coefficient computation unit, a candidate hidden-state computation unit, and a state update unit. Signed weights are represented by positive-negative differential memristor conductance arrays, and point-wise recurrent weights are mapped only to their corresponding channel positions. To reduce the mismatch between software training and circuit implementation, PWL activation-aware training is adopted, where PWL-Sigmoid and PWL-Tanh functions consistent with the circuit implementation are used during training. After training, the weights are quantized to 8 bits and mapped to memristor conductance states. The proposed model is evaluated on Adding Problem, Row-wise MNIST, IMDB, and UCI HAR. For UCI HAR, the original nine-channel smartphone inertial signals with 128 time steps are used to evaluate six-class human activity recognition in a realistic edge-sensing scenario. The corresponding memristor-based circuit is analyzed under a 40 nm process condition.Results and Discussions Compared with LSTM and GRU, the two-layer P-SGRU reduces the number of hidden-to-hidden recurrent parameters by 98.44% and 97.92%, respectively, and removes full hidden-to-hidden vector-matrix multiplication branches (Table 2). On the tested sequence tasks, P-SGRU-2L achieves 98.21%±0.20% accuracy on Row-wise MNIST and 86.85%±0.13% accuracy on IMDB, while the single-layer P-SGRU is selected for circuit implementation considering the model scale and circuit overhead of resource-constrained edge systems (Table 2). On UCI HAR, P-SGRU-2L achieves 91.87%±0.94% accuracy and 91.94%±0.94% macro-F1 with 10,246 parameters (Table 2). After being mapped to the proposed memristor-based circuit, the single-layer P-SGRU achieves circuit-level accuracies of 95.03%±0.06% and 86.76%±0.05% on Row-wise MNIST and IMDB, respectively, with a maximum accuracy loss of only 0.02% compared with the software model. Under the 40 nm process condition, the proposed P-SGRU circuit shows lower or comparable delay under different task configurations (Table 3). In addition, the single-channel, single-time-step update simulation shows that the critical-path delay is reduced from 524.5 ps in GRU to 177.9 ps in P-SGRU, corresponding to a 66.1% reduction, verifying the effect of removing the serial dependency between the retention-coefficient branch and the candidate hidden-state branch.Conclusions This paper addresses efficient temporal inference in resource-constrained edge systems by proposing P-SGRU and its memristor-based in-memory computing circuit implementation. The proposed P-SGRU replaces the fully connected hidden-to-hidden transformation with point-wise recurrent modulation, thereby reducing the parameter scale and computational complexity of the recurrent path. Meanwhile, by decoupling the retention-coefficient branch from the candidate hidden-state branch, P-SGRU improves intra-step computational parallelism and shortens the recurrent update path. Experimental results on Adding Problem, Row-wise MNIST, IMDB, and UCI HAR show that P-SGRU maintains favorable sequence modeling performance while significantly simplifying the recurrent structure. In particular, the UCI HAR results demonstrate that the stacked P-SGRU can effectively model real multi-channel inertial sequences while retaining a lower parameter count than conventional gated recurrent models. Circuit-level evaluation further demonstrates that the P-SGRU circuit after hardware mapping achieves inference results close to those of the software model, and the single-channel single-time-step update critical-path delay is reduced by about 66.1% compared with GRU under the 40 nm process condition. These results indicate that P-SGRU provides a lightweight and efficient algorithm-circuit co-design solution for edge temporal inference. Future work will further extend P-SGRU to more complex edge temporal tasks and explore its integration with high-density in-memory computing arrays and edge intelligence systems for low-power and low-latency temporal inference.
- Memristor,
- Recurrent Neural Network (RNN),
- Point-Wise Single-Gate Recurrent Unit (P-SGRU),
- In-Memory Computing,
- Edge Temporal Inference

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References(18)

References

[1]	ROCHA A, MONTEIRO M, MATTOS C, et al. Edge AI for Internet of Medical Things: A literature review[J]. Computers and Electrical Engineering, 2024, 116: 109202. doi: 10.1016/j.compeleceng.2024.109202.
[2]	GUO Qi, ZHAO Baolin, SONG Mingchen, et al. A survey of deep learning for time series forecasting: Taxonomy, analysis and future directions[J]. IEEE Transactions on Knowledge and Data Engineering, 2026, 38(5): 2541–2560. doi: 10.1109/TKDE.2026.3671378.
[3]	周维新, 高肇岗, 肖宛昂. 面向可穿戴式的基于LSTM神经网络的智能心音异常诊断芯片[J]. 电子与信息学报, 2024, 46(2): 555–563. doi: 10.11999/JEIT230934. ZHOU Weixin, GAO Zhaogang, and XIAO Wan’ang. Intelligent heart sound abnormal diagnosis chip based on LSTM for wearable applications[J]. Journal of Electronics & Information Technology, 2024, 46(2): 555–563. doi: 10.11999/JEIT230934.
[4]	MEHRISH A, MAJUMDER N, BHARADWAJ R, et al. A review of deep learning techniques for speech processing[J]. Information Fusion, 2023, 99: 101869. doi: 10.1016/j.inffus.2023.101869.
[5]	MAO Yanying, LIU Qun, and ZHANG Yu. Sentiment analysis methods, applications, and challenges: A systematic literature review[J]. Journal of King Saud University-Computer and Information Sciences, 2024, 36(4): 102048. doi: 10.1016/j.jksuci.2024.102048.
[6]	任利强, 贾舒宜, 王海鹏, 等. 基于深度学习的时间序列分类研究综述[J]. 电子与信息学报, 2024, 46(8): 3094–3116. doi: 10.11999/JEIT231222. REN Liqiang, JIA Shuyi, WANG Haipeng, et al. A review of research on time series classification based on deep learning[J]. Journal of Electronics & Information Technology, 2024, 46(8): 3094–3116. doi: 10.11999/JEIT231222.
[7]	GREFF K, SRIVASTAVA R K, KOUTNÍK J, et al. LSTM: A search space odyssey[J]. IEEE Transactions on Neural Networks and Learning Systems, 2017, 28(10): 2222–2232. doi: 10.1109/TNNLS.2016.2582924.
[8]	ZHOU Guobing, WU Jianxin, ZHANG Chenlin, et al. Minimal gated unit for recurrent neural networks[J]. International Journal of Automation and Computing, 2016, 13(3): 226–234. doi: 10.1007/s11633-016-1006-2.
[9]	LI Shuai, LI Wanqing, COOK C, et al. Independently recurrent neural network (IndRNN): Building a longer and deeper RNN[C]. Proceedings of the 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition, Salt Lake City, USA, 2018: 5457–5466. doi: 10.1109/CVPR.2018.00572.
[10]	HASSAAN Z A, YACOUB M H, and SAID L A. Gated recurrent unit accelerators for financial time series prediction on field-programmable gate array[J]. Engineering Applications of Artificial Intelligence, 2025, 162: 112534. doi: 10.1016/j.engappai.2025.112534.
[11]	AGUIRRE F, SEBASTIAN A, LE GALLO M, et al. Hardware implementation of memristor-based artificial neural networks[J]. Nature Communications, 2024, 15(1): 1974. doi: 10.1038/s41467-024-45670-9.
[12]	谢力凡, 卫松涛, 姚鹏, 等. 基于反向编程策略的高并行高精度RRAM存算一体芯片[J]. 电子与信息学报, 2026, 48(5): 1875–1883. doi: 10.11999/JEIT251174. XIE Lifan, WEI Songtao, YAO Peng, et al. A fast and accurate programming strategy for analog in-memory computing validated with a transposable RRAM Macro and 0.64% fully-parallel RMS error[J]. Journal of Electronics & Information Technology, 2026, 48(5): 1875–1883. doi: 10.11999/JEIT251174.
[13]	WANG Shiqing and SUN Zhong. Dual in-memory computing of matrix-vector multiplication for accelerating neural networks[J]. Device, 2024, 2(12): 100546. doi: 10.1016/j.device.2024.100546.
[14]	李源堃, 王泽, 张清天, 等. NAS4CIM: 面向忆阻器存算一体芯片的神经网络结构搜索框架[J]. 电子与信息学报, 2025, 47(12): 4948–4958. doi: 10.11999/JEIT250978. LI Yuankun, WANG Ze, ZHANG Qingtian, et al. NAS4CIM: Tailored neural network architecture search for RRAM-based compute-in-memory chips[J]. Journal of Electronics & Information Technology, 2025, 47(12): 4948–4958. doi: 10.11999/JEIT250978.
[15]	YANG Le, LEI Jun, CHENG Ming, et al. Memristor-based circuit design of BiLSTM network[J]. Neural Networks, 2025, 181: 106780. doi: 10.1016/j.neunet.2024.106780.
[16]	WANG Yanfeng, SONG Yibo, CHEN Yu, et al. Memristor-based circuit optimized gate recurrent unit for wind power prediction[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2026, 73(3): 1828–1839. doi: 10.1109/TCSI.2025.3602022.
[17]	ZHANG Zhang, CHEN Qilai, HAN Tingting, et al. Memristor-based circuit demonstration of gated recurrent unit for predictable neural network[J]. IEEE Transactions on Electron Devices, 2022, 69(12): 6763–6768. doi: 10.1109/TED.2022.3217116.
[18]	LEI Tao, ZHANG Yu, WANG S I, et al. Simple recurrent units for highly parallelizable recurrence[C]. Proceedings of the 2018 Conference on Empirical Methods in Natural Language Processing, Brussels, Belgium, 2018: 4470–4481. doi: 10.18653/v1/D18-1477.