A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration

ZHOU Jing; ZHANG Shengbing; CHEN Lei; FENG Hanxu; WANG Shuo; TIAN Chunsheng

doi:10.11999/JEIT260609

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ZHOU Jing, ZHANG Shengbing, CHEN Lei, FENG Hanxu, WANG Shuo, TIAN Chunsheng. A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260609

Citation:

ZHOU Jing, ZHANG Shengbing, CHEN Lei, FENG Hanxu, WANG Shuo, TIAN Chunsheng. A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260609

Citation:

ZHOU Jing, ZHANG Shengbing, CHEN Lei, FENG Hanxu, WANG Shuo, TIAN Chunsheng. A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260609

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A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration

doi: 10.11999/JEIT260609 cstr: 32379.14.JEIT260609

1.
Northwestern Polytechnical University, Xi’an 710072, China
2.
Beijing Microelectronics Technology Institution, Beijing 100070, China

Received Date: 2026-05-14
Accepted Date: 2026-07-29
Rev Recd Date: 2026-07-28

Available Online: 2026-08-08

Abstract

Abstract

Objective Architecture parameters of commercial off-the-shelf Field-Programmable Gate Arrays (FPGAs) are fixed by vendors and reused across products. Embedded FPGAs (eFPGAs), in contrast, allow architects to select architecture parameters according to specific application requirements. The LUT input count K, the number of LUTs per cluster N, the interconnect topology, and the types of heterogeneous tiles can therefore be configured for the target application. Architecture design space exploration thus becomes an engineering task in which tens to hundreds of architectures may need to be generated and evaluated before a suitable configuration is selected. Existing architecture description practices rely largely on manually written architecture files and batch scripts. After each parameter change, shared fields across multiple backend toolchains must be updated and aligned manually, making large-scale architecture exploration difficult to support. To address this problem, a parametric architecture description framework is proposed for unified description across multiple backend toolchains. Architecture parameters are organized into three layers according to their independence: process invariants, coupled parameters, and independent parameters. Architecture descriptions for different backends are automatically derived from the same source object through independent derivation functions. The framework currently supports VPR, OpenFPGA, and Yosys and has been extended to COFFE. Its operation is validated across the complete toolchain. Based on the framework, a parameter-sweep design space exploration method is developed, and an open Quality of Results (QoR) dataset covering five application domains and 64 benchmark circuits, including homogeneous and heterogeneous architectures, is released as a public benchmark. Methods HorizonArch, the proposed parametric architecture description framework, organizes architecture parameters into three layers according to parameter independence (Table 1). L0 contains process invariants that are fixed once the technology node is determined. L1 contains coupled parameters, including K, N, tier, segment length, switch block type, and channel connectivity, for which a single parameter change can trigger updates across multiple fields and backend architecture descriptions. L2 contains independent parameters that can be specified separately. Architecture construction is formalized by an operator B that maps a parameter vector p to a complete architecture object (Fig. 4). Five formal rules are imposed: parameter completeness (R1), fragment independence (R2), type compatibility (R3), explicit coupling (R4), and static checkability (R5). Each backend architecture description is then derived by an independent derivation function from the same source object. Thus, adding a new backend requires only an additional view rather than modifications throughout the existing description structure. Field-level validation and cross-field validation are performed when the architecture object is loaded, before any backend tool is invoked. The class structure (Fig. 3) divides the architecture description into synthesis, circuit, and layout views, with each semantic element declared only once. Three extension levels are defined: G1 adds a black-box model, G2 extends the value set of an existing coupled parameter, and G3 adds a new coupled parameter together with its constrained value set. Based on this framework, a parameter-sweep design space exploration method is developed to scan the (K, N) parameter grid and heterogeneous tile configurations. Each configuration is evaluated using three QoR metrics: area, Critical-Path Delay (CPD), and Area-Delay Product (ADP). Results and Discussions End-to-end validation shows that a single source description consistently generates architecture descriptions for VPR, OpenFPGA, and Yosys. COFFE is connected and verified at the interface layer, including SPICE simulation startup (Table 4, Table 5). The G1, G2, and G3 extension experiments pass all cross-field checks. The design space exploration results show different preferences among area, CPD, and ADP across the (K, N) parameter space (Figs. 5 and 6). Area favors smaller K values, with K=4 and N=4 providing favorable area and ADP performance for a large proportion of circuits. CPD, in contrast, favors larger K and N values, with optimal configurations concentrated near (K, N)=(8, 10) and (7, 10). Across the twenty (K, N) configurations, the relative-range distribution shows that parameter selection has a much greater effect on area and ADP than on CPD (Table 6). The mean relative ranges are 50.9% for CPD, 675.1% for area, and 516.3% for ADP. A comparison of default configurations (Table 7) shows that K=4 and N=4 achieves the minimum ADP for 67.9% of the circuits and has an average ADP deviation of 5.8%, although its average CPD deviation reaches 47.9%. In contrast, K=8 and N=10 reduces the average CPD deviation to 5.9%, with 30.8% of the circuits achieving the CPD optimum, but increases the average area and ADP deviations to 673.2% and 487.0%, respectively. A random-forest cross-domain surrogate achieves a top-5 accuracy of approximately 65%. Therefore, parameter sweeping remains necessary when strict design targets are imposed. Conclusions HorizonArch, a parametric architecture description framework for eFPGA exploration, is developed and validated. The framework generates VPR, OpenFPGA, and Yosys backend architecture descriptions from a single source object and provides an extensible interface for COFFE. The parameter-sweep exploration shows that area and CPD favor opposite regions of the (K, N) parameter space. Therefore, eFPGA architecture parameters should be selected according to explicit design targets rather than fixed default values. An open QoR dataset covering five application domains and 64 benchmark circuits is also released as a reusable benchmark for eFPGA architecture design space exploration. Future work will complete the COFFE SPICE topology-rewriting component, refit the routing-area coefficient using measured data, and explore more efficient design space exploration strategies.

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References(16)

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