An ECO Repair Method for Max Transition Violations in Multi-Load Nets

FAN Lingyan; XU Xinchen; HUANG Cankun; SHEN Zhengnuo; DENG Jiangxia; LIU Hailuan

doi:10.11999/JEIT260600

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FAN Lingyan, XU Xinchen, HUANG Cankun, SHEN Zhengnuo, DENG Jiangxia, LIU Hailuan. An ECO Repair Method for Max Transition Violations in Multi-Load Nets[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260600

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FAN Lingyan, XU Xinchen, HUANG Cankun, SHEN Zhengnuo, DENG Jiangxia, LIU Hailuan. An ECO Repair Method for Max Transition Violations in Multi-Load Nets[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260600

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An ECO Repair Method for Max Transition Violations in Multi-Load Nets

doi: 10.11999/JEIT260600 cstr: 32379.14.JEIT260600

1.
Microelectronics Research Institute, Hangzhou Dianzi University, Hangzhou 310018, China
2.
Hangzhou Hualan Microelectronique Co., Ltd. Hangzhou 311210, China

Funds: The National Natural Science Foundation of China(U22A2071)

Received Date: 2026-05-14
Accepted Date: 2026-08-13
Rev Recd Date: 2026-08-13

Available Online: 2026-08-25

Abstract

Abstract

Objective Max transition violations in digital integrated circuit physical design may increase gate delay, reduce timing margin, and introduce additional power-consumption and signal-integrity risks. With technology scaling and the increasing complexity of high-performance SoC and CPU designs, long interconnects and heavy effective loads make such violations more prominent in post-routing optimization and ECO stages. Conventional repair methods usually rely on manual analysis or global heuristics, such as total-wire-length-ratio-based buffer insertion, which may lead to low repair efficiency, inaccurate repair targeting, and redundant buffer insertion in multi-load nets. Although these approaches can alleviate some violations in simple cases, they often fail to accurately identify the real violating branches in multi-load nets. As a result, repair targeting becomes insufficient and redundant buffer insertion is likely to occur. To address these limitations, a path-level buffer insertion method is proposed for max transition violation repair in multi-load nets. Methods The proposed method first reconstructs the physical topology of the target net from routing information extracted from the Design Exchange Format (DEF) file. Routing endpoints, turning points, and via connection points are abstracted as physical nodes with coordinate and metal-layer attributes, and a weighted undirected graph is established to preserve branch structures and cross-layer connectivity (Fig. 3). To reduce the influence of small coordinate deviations, a spatial-tolerance-based node merging strategy is introduced during graph construction. Since the violation coordinates reported by timing analysis tools may not lie exactly on valid routed segments, a vector-projection-based coordinate snapping strategy is then adopted to align logical violation coordinates with the actual physical topology (Fig. 4). After endpoint binding, the actual physical propagation path from the driver to each violating load is recovered by Dijkstra shortest-path search. Based on the Elmore-model intuition that inserting a buffer near the midpoint of a long interconnect can effectively segment the distributed RC load, the midpoint of each recovered path is selected as the initial candidate insertion point. The exact insertion coordinate is obtained by accumulating segment lengths along the path and interpolating on the segment where half of the total path length is reached. To improve robustness, the initial candidate point is further expanded into an effective candidate interval with a spatial tolerance factor. For multi-load nets, different violating branches may share long common physical segments. Therefore, an interval-intersection-based shared-buffer optimization strategy is introduced to merge overlapping candidate intervals into shared insertion regions, thereby reducing redundant buffer insertion (Fig. 5-Fig. 7). Results and Discussions Experiments are conducted on five designs, including CPU, SAS, RAID, PCIe, and HBA, implemented in the UMC 28 nm process. Synopsys IC Compiler II is used for physical implementation, and PrimeTime is used for timing analysis. A violation-margin threshold of -8 ps is adopted, and only paths below this threshold are included in the repair and evaluation. The complete ECO flow retains the existing repair method for single-load nets and applies the proposed path-level method to multi-load nets. To illustrate the repair mechanism, a representative multi-load violating net is selected for detailed analysis. The net contains one driver and fourteen loads, among which thirteen violating load paths share a long common routed trunk and exhibit max transition violation margins ranging from -75.2 ps to -38.3 ps. If these paths are repaired independently, thirteen nearby buffer insertion demands are generated on the shared trunk. After interval-intersection-based merging, one shared buffer is sufficient to repair all thirteen violating paths jointly (Fig. 8). This case study indicates that path recovery improves repair targeting, while shared-buffer optimization improves resource efficiency. Across the five designs, the complete ECO flow reduces the total number of max transition violations from 10,616 to 108, corresponding to an overall repair rate of 98.98% (Table 1). The CPU, SAS, and RAID designs are completely repaired, while only 17 and 91 violations remain in PCIe and HBA, respectively. Among the 8,216 multi-load violating paths, 8,166 are successfully repaired, corresponding to a multi-load violation repair rate of 99.39%. If these successfully repaired paths were handled independently, 8,166 buffer insertions would be required. After shared-buffer optimization, only 1,548 buffers are inserted, giving an overall compression ratio of 81.04%. The setup worst negative slack, total negative slack, and number of violating paths remain generally stable before and after repair, with only minor fluctuations observed in individual designs (Table 2). These results show that the repair flow does not cause obvious degradation in setup timing quality. Further analysis indicates that the residual violations in PCIe and HBA mainly occur when candidate buffer locations fall inside standard-cell placement blockages around hard macros or IP cores. Metal routing is allowed through these regions, but buffers cannot be legally placed, revealing a current limitation in the physical-feasibility handling of candidate insertion locations. Conclusions A path-level buffer insertion method is proposed for max transition violation repair in multi-load nets. By combining physical topology reconstruction, violation-coordinate snapping, shortest-path-based path recovery, midpoint-guided candidate generation, and interval-intersection-based shared-buffer optimization, the proposed method improves repair targeting and reduces redundant buffer insertion. Experimental results on five designs show that the complete ECO flow reduces the number of max transition violations from 10,616 to 108, achieving an overall repair rate of 98.98%. Among the 8,216 multi-load violating paths, 8,166 are successfully repaired, corresponding to a repair rate of 99.39%. For these successfully repaired paths, shared-buffer optimization reduces the number of buffer insertion demands from 8,166 to 1,548, corresponding to a compression ratio of 81.04%, without causing obvious degradation in setup timing quality. The remaining violations are mainly associated with standard-cell placement blockages around hard macros or IP cores, indicating that the physical-feasibility handling of candidate insertion locations should be further improved.
- max transition violation,
- ECO repair,
- shared buffer optimization

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References(16)

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