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YU Tianyang, WU Bi, LIU Weiqiang. Efficient Hyperdimensional Computing Accelerator Design for Chinese Text Classification[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260556
Citation: YU Tianyang, WU Bi, LIU Weiqiang. Efficient Hyperdimensional Computing Accelerator Design for Chinese Text Classification[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260556

Efficient Hyperdimensional Computing Accelerator Design for Chinese Text Classification

doi: 10.11999/JEIT260556 cstr: 32379.14.JEIT260556
Funds:  The National Natural Science Foundation of China (62425404, 92364201, 62522406), Basic Research Program of Jiangsu (BK20253023)
  • Received Date: 2026-05-06
  • Accepted Date: 2026-07-28
  • Rev Recd Date: 2026-07-16
  • Available Online: 2026-08-07
  •   Objective  With the proliferation of edge computing in the Internet of Things (IoT), smart wearables, and offline terminals, low-latency and privacy-preserving Chinese text analysis on local devices has become a core requirement. Although neural network-based and Transformer-based language models achieve high accuracy, their large parameter sizes and computational demands make them difficult to deploy on power- and storage-constrained edge devices. HyperDimensional Computing (HDC), an emerging brain-inspired computing paradigm, represents text using 2 k~10 k-dimensional hypervectors and employs lightweight encoding and querying mechanisms instead of complex multilayer networks, providing a hardware-friendly approach for edge-side text processing. However, existing HDC studies have mainly focused on alphabetic writing systems such as English, in which a limited set of letters is sufficient for N-gram encoding. For Chinese, which contains thousands of commonly used characters, directly applying these methods would require a large number of base hypervectors, resulting in substantial storage overhead and weakening the lightweight advantage of HDC. This paper aims to address this limitation by proposing an efficient character encoding method and a dedicated HDC framework with hardware acceleration for Chinese text classification.  Methods  Based on the glyph structure of Chinese characters, a hyperdimensional encoding method based on character glyph structure is proposed. Specifically, the encoding process of the Wubi input method is reverse-engineered to decompose each Chinese character into an equivalent Wubi letter sequence for efficient hyperdimensional encoding. A retrieval library covering 3 500 commonly used Chinese characters, as defined in the General Standard Chinese Characters Table issued by the Ministry of Education of the People’s Republic of China, is constructed. For each character, the Wubi library is queried to obtain a letter sequence of length 3 or 4, with each letter mapped to a base hypervector. Cyclic shift and binding operations are then applied to the base hypervectors of consecutive letters. This produces a character-level hypervector that captures both letter identity and positional order information, thereby avoiding confusion caused by different letter permutations. Compared with directly assigning an independent hypervector to each Chinese character, the proposed method reduces the storage requirement for base hypervectors by more than 95% (Table 1). Building on this character encoding method, the HDChinese framework is developed to support inference, training, and retraining. During inference, the sentence-level hypervector obtained by bundling all character hypervectors queries the class hypervectors using cosine similarity. Because the hypervectors are binary, the inner-product operation is efficiently implemented using XNOR logic. During training, class hypervectors are generated by bundling sentence hypervectors belonging to the same class and applying sign-based binarization. During retraining, the nonbinary class hypervectors are iteratively updated using misclassified samples with a learning rate of 0.25, thereby reducing the effect of outlier hypervectors on the cluster center. Furthermore, a dedicated hardware accelerator architecture is designed for HDChinese. The architecture comprises three main modules: an encoding module, a querying module, and a class hypervector update module. These modules can be selectively activated to support inference, training, and retraining modes, respectively (Fig. 2). The accelerator is prototyped on an Ultra96v2 FPGA development board equipped with a Xilinx ZYNQ System on Chip (SoC).  Results and Discussions  Four open-source Chinese text classification datasets covering binary and multiclass tasks are used for evaluation (Table 2). The Wubi-based encoding method achieves higher accuracy than the Pinyin-based method on all four datasets and reduces the storage requirement by 31.46% (Table 4). Ignoring uncommon Chinese characters, which occur at an average frequency of less than 0.5%, has a negligible effect on accuracy (Table 4). A hypervector dimension of 2 k is selected because increasing the dimension beyond 2 k provides no significant accuracy improvement (Fig. 3). FPGA measurements show that HDChinese achieves a model size of approximately 16 kB, representing a reduction of more than 99% compared with k-Nearest Neighbor (kNN), Support Vector Machine (SVM), and random forest models (Table 7). Compared with SVM and random forest, the proposed accelerator reduces inference time by 6.67%~47.25% and total training time by 4.91%~77.36%. After retraining, the classification accuracy reaches levels comparable to those of the comparison methods (Fig. 4, Table 7). The kB-scale model also enables operation without external memory chips, whereas the comparison methods require more than 400 MB of runtime memory. At 100 MHz, the FPGA implementation consumes 0.278 W, providing the most favorable trade-off between throughput and power consumption (Table 6).  Conclusions  A hyperdimensional encoding method based on Chinese character glyph structure is proposed to address the incompatibility between existing HDC methods and Chinese text. The HDChinese framework and its dedicated hardware accelerator reduce model complexity by more than 99% while maintaining competitive classification accuracy. Training time is reduced by 4.91%~77.36%, and inference time is reduced by 6.67%~47.25%. The proposed approach achieves a favorable balance between accuracy and computational and storage overhead, providing a hardware solution for Chinese text analysis on edge devices.
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