A Novel TDMOSFET and Its Neural Network Modeling for Ternary Logic Applications

LU Bin; LU Haoran; ZHAO Xiaohong; DI Jiayu; XING Linlin

doi:10.11999/JEIT260413

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LU Bin, LU Haoran, ZHAO Xiaohong, DI Jiayu, XING Linlin. A Novel TDMOSFET and Its Neural Network Modeling for Ternary Logic Applications[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260413

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LU Bin, LU Haoran, ZHAO Xiaohong, DI Jiayu, XING Linlin. A Novel TDMOSFET and Its Neural Network Modeling for Ternary Logic Applications[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260413

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A Novel TDMOSFET and Its Neural Network Modeling for Ternary Logic Applications

doi: 10.11999/JEIT260413 cstr: 32379.14.JEIT260413

LU Bin^1
,,
LU Haoran^2
,,
ZHAO Xiaohong^{3
,
,},
DI Jiayu^1
,,
XING Linlin^2
,

1.
School of Computer Science and Artificial Intelligence, Shanxi Normal University, Taiyuan 030031, China
2.
School of Physics and Information Engineering, Shanxi Normal University, Taiyuan 030031, China
3.
School of Aeronautical Engineering, Air Force Engineering University, Xi’an 710071, China

Funds: General Project of Natural Science Research of Shanxi Province (Grant Number: 202403021211225) and Postgraduate Education Innovation Program of Shanxi Province (Grant Number: 2025XS353)

Received Date: 2026-04-08
Accepted Date: 2026-08-10
Rev Recd Date: 2026-08-10

Available Online: 2026-08-13

Abstract

Abstract

Objective Complementary metal-oxide-semiconductor (CMOS) technology is continuously improving, moving toward smaller size and higher integration. As circuit integration increases, short-channel effects and other phenomena lead to a significant rise in leakage current in MOSFET devices, resulting in higher static power consumption. Against the backdrop of rapid advancements in artificial intelligence, traditional binary logic chips face severe limitations in computing and storing massive amounts of data. To meet the demands for higher efficiency, greater density, and lower power consumption, ternary logic technology has attracted widespread attention from researchers. Compared with traditional binary logic, ternary logic offers advantages such as higher information density and lower system complexity. However, the current design of ternary logic circuits faces several challenges, including the need for a large number of components, the involvement of passive elements, and poor compatibility with conventional CMOS processes. Methods To address these issues, this paper proposes a novel Tunneling and Drift-Diffusion Metal-Oxide-Semiconductor Field-Effect Transistor (TDMOSFET) that integrates both quantum tunneling and drift-diffusion mechanisms. This device features a constant off-state circuit characteristic, making it suitable for ternary logic applications. The working principle of the TDMOSFET is analyzed in detail, and an artificial neural network (ANN) is employed to model the device. The established ANN model can accurately simulate the current-voltage (IV) and capacitance-voltage (CV) characteristics of the device. Furthermore, the ANN model is converted into a Verilog-A program and embedded into HSPICE to simulate basic ternary logic circuits, including the Standard Ternary Inverter (STI), Negative Ternary Inverter (NTI), Positive Ternary Inverter (PTI), Ternary NOT-AND gate (T-NAND), and Ternary NOT-OR gate (T-NOR). Results and Discussions The well-trained ANN model can accurately predicted the current-voltage and capacitance-voltage performance. The maximum relative errors of the ANN model compared with the TCAD results are 39.43%, 5.05%, and 14.19% for the drain current IDS, gate-drain capacitance CGD and gate-source capacitance CGS, respectively, and the average relative errors are 0.46%, 0.69%, and 0.51%, respectively. Moreover, the well-trained ANN is successfully converted into Verilog-A programs and demonstrates excellent compatibility with widely used HSPICE tools. Based on the models, the basical units including the STI, NTI, PTI, T-NAND and T-NOR are simulated. The designed ternary logic circuits eliminate the need for passive elements and are compatible with conventional CMOS processes. Conclusions This paper proposes a novel TDMOSFET. It maintains compatibility with CMOS fabrication processes, thereby simplifying the manufacturing workflow and reducing both cost and integration complexity. The proposed ternary logic circuits based on the TDMOSFETs achieve ternary operation without increasing the number of transistors, relying on passive components, or requiring multi-valued supply voltages., offering significant reference value for future research. Furthermore, the “TCAD→ANN Modeling→Verilog-A Language→HSPICE Simulation” methodology established in this work can also be applied to the investigation of other emerging semiconductor devices.
- Quantum Tunneling,
- Ternary Logic,
- TDMOSFET,
- Neural Network Modeling

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References(32)

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