FPGA Hybrid Programmable Logic Block Architecture for Highly Efficient Resource Utilization

WANG Yanlin; GAO Lijiang; YANG Haigang

doi:10.11999/JEIT260108

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WANG Yanlin, GAO Lijiang, YANG Haigang. FPGA Hybrid Programmable Logic Block Architecture for Highly Efficient Resource Utilization[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260108

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WANG Yanlin, GAO Lijiang, YANG Haigang. FPGA Hybrid Programmable Logic Block Architecture for Highly Efficient Resource Utilization[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260108

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FPGA Hybrid Programmable Logic Block Architecture for Highly Efficient Resource Utilization

doi: 10.11999/JEIT260108 cstr: 32379.14.JEIT260108

WANG Yanlin^{1, 2},
GAO Lijiang³,
YANG Haigang^{2
,
,}

1.
Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, China
2.
University of Chinese Academy of Sciences, Beijing 100094, China
3.
Beijing Zhongke Shengxin Technology Co., Ltd., Beijing 100081, China

Funds: The National Natural Science Foundation of China (61876172)

Received Date: 2026-01-28
Accepted Date: 2026-02-14
Rev Recd Date: 2026-02-14

Available Online: 2026-03-04

Abstract

Abstract

Six-input Look-Up Tables (6-LUTs) are widely used in commercial Field-Programmable Gate Arrays (FPGAs) to construct programmable logic blocks. However, related experiments show that their average utilization in circuits is less than 30%, which leads to substantial waste of programmable resources. In this paper, 6-LUTs are fractured according to fracturable factors and then recombined at different granularities to construct several new Hybrid Basic Logic Elements (HBLEs). Based on these HBLEs, several novel Hybrid Programmable Logic Block (HPLB) architectures are proposed. The programmable logic blocks in Xilinx devices are then replaced with these HPLB architectures. Concurrently, a statistical evaluation algorithm for the mapped netlist is proposed. Finally, several HPLB architectures are experimentally verified and evaluated. Experimental results for the three enhanced architectures show that the HPLBs achieve an average area reduction of more than 30% compared with Xilinx PLBs, without increasing the number of input ports. Among them, the hybrid HPLB architecture with a fracturable factor of N = 3 achieves the best overall optimization when both HPLB utilization and area reduction are considered. Based on the MCNC and VTR benchmarks, the proposed architecture results in average HPLB count increases of 8.27% and 27.64%, respectively, while improving programmable resource utilization. Objective Currently, modern commercial Field-Programmable Gate Array (FPGA) architectures use Six-input Look-Up Tables (6-LUTs) as the fundamental building blocks of basic logic elements. Experimental results show that when circuits are mapped to 6-LUT-based basic logic elements, only about 30% of the logic elements are ultimately implemented as 6-LUTs. When 6-LUTs are used to implement functions with fewer than six inputs, more than half of the logic resources are wasted. This leads to substantial underutilization of programmable resources. Experimental data show that a circuit design mapped to 100 4-LUTs can be fractured into 78 6-LUTs during 6-LUT mapping, with a {6,5,4,3,2}-LUT function distribution of {23,32,17,9,13}. These results indicate that only about 25% of the 6-LUTs are assigned to 6-input functions, whereas the remaining 6-LUTs are underutilized. This further demonstrates the inefficiency of technology mapping for LUTs with a large input size K.Methods The fracturable factor N, defined as the number of sub-LUTs that can be obtained from a single LUT, characterizes the fracturable and reconfigurable nature of LUT architectures in FPGAs. To address the low resource utilization described above, a 6-LUT is fractured into several granularities according to the fracturable factor. Three novel hybrid-granularity divisible logic structures are then constructed by reconnecting and reconfiguring the resulting sub-LUTs with additional input ports and multiplexer modules. The optimization effects of these three Hybrid Basic Logic Element (HBLE) topologies on FPGA performance are then investigated. The HBLE2 structure consists of one intact 6-LUT and one divisible 6-LUT split into two 5-LUTs with a fracturable factor of N = 2. The HBLE3 structure consists of one intact 6-LUT and one divisible 6-LUT split into one 5-LUT and two 4-LUTs with a fracturable factor of N = 3. The HBLE4 structure consists of one intact 6-LUT and one divisible 6-LUT split into four 4-LUTs with a fracturable factor of N = 4. All three HBLE structures support adder units and allow either latched output or direct combinational logic output. They also support direct latched output without passing through combinational logic. A Hybrid Programmable Logic Block (HPLB) is formed by combining several HBLEs. Two widely used academic benchmark sets, the MCNC circuit set and the VTR circuit set, are selected for experimental evaluation. Each circuit set is mapped onto a Xilinx Virtex-7 FPGA. The mapped netlist is then analyzed to count the types and numbers of LUTs used. After the data are organized with the corresponding greedy algorithms, the minimum number of Configurable Logic Blocks (CLBs) required is determined. Because each Xilinx CLB contains eight 6-LUTs, the greedy algorithm uses the total LUT number fractured by 8 to estimate the minimum number of CLBs required after benchmark mapping. To ensure comparable conditions, each structure is also reorganized with the greedy algorithm after the Xilinx CLB structure is replaced by the HPLB structure proposed in this study. This yields the minimum number of HPLBs required. In practical packing, not every LUT in the mapped CLBs can be used because of routing constraints. Therefore, the optimized result obtained after greedy restructuring represents the theoretical lower bound under ideal optimization conditions. Results and Discussions For the MCNC circuit set, replacing CLB structures with HPLBs reduces the average number of required blocks by about 8% for both the HPLB2 and HPLB3 structures. However, the HPLB4 structure increases the required block count by more than 30% on average. For the VTR circuit set, fewer HPLBs are required than CLBs after replacement. On average, the counts for HPLB2 and HPLB4 decrease by less than 10%, whereas the count for HPLB3 decreases by about 30%. This allows more efficient SRAM scheduling and fuller use of input pins. In contrast, the uniform CLB structure requires more CLBs when functions with a small LUT input size K are implemented because of resource waste. According to the post-mapping HPLB counts, the HPLB4 structure performs less effectively than the HPLB3 structure. Analysis of post-mapping area optimization shows that both the MCNC and VTR circuit sets achieve average area reduction ratios of more than 30%. On the MCNC benchmark set, all three HPLB structures achieve area optimization ratios of about 31%. On the VTR benchmark set, the optimization effects differ: HPLB2 achieves an average area reduction of 30.63%, whereas HPLB4 achieves an average reduction of 51.21%. HPLB3 achieves a 45.22% area reduction, which is slightly lower than that of HPLB4. Detailed analysis of the area optimization results shows that a higher fracturable factor N provides greater benefits for integrating small-scale LUTs in circuits, resulting in larger area reduction ratios in the enhanced architectures. Conclusions To address the low resource utilization of 6-LUTs, this study proposes three HPLB enhancement architectures based on split granularity. These HPLBs replace the Xilinx CLB structure, and an evaluation procedure and matching algorithms are established to examine the advantages of the proposed structures in resource utilization. Evaluation experiments based on the MCNC and VTR benchmark suites show that although HPLB4 achieves substantial area optimization, it also requires more HPLBs, which increases interconnect area. Both HPLB2 and HPLB3 achieve average area reductions of more than 30%. As the scale of the test circuits increases, HPLB3 provides a greater increase in HPLB count and a stronger area optimization effect than HPLB2. Therefore, after the CLB structure is replaced, HPLB3 provides a better balance between HPLB usage and area optimization, and substantially improves the utilization of programmable resources.
- Field programmable gate array,
- Programmable logic block,
- Look-up table,
- Mapping,
- Fracturable factor

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References(19)

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