V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration

LI Tuo; WANG Changhong; CHENG Chao; LI Guoqing; LI Nanjun

doi:10.11999/JEIT260073

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LI Tuo, WANG Changhong, CHENG Chao, LI Guoqing, LI Nanjun. V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260073

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LI Tuo, WANG Changhong, CHENG Chao, LI Guoqing, LI Nanjun. V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260073

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V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration

doi: 10.11999/JEIT260073 cstr: 32379.14.JEIT260073

1.
Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co., Ltd., Jinan 250000, China
2.
Jinan Maxwell Smart Technology Co., Ltd., Jinan 250000, China

Received Date: 2026-01-21
Accepted Date: 2026-09-17
Rev Recd Date: 2026-09-17

Available Online: 2026-09-24

Abstract

Abstract

Objective Large Language Models (LLMs) can assist with Register Transfer Level (RTL) code generation. However, processor-level designs require coordination among independently generated control, datapath, top-level integration, and verification modules. Inconsistencies in port names, directions, widths, or signal types can prevent compilation and require manual diagnosis for repair. This study proposes V-Agent, a protocol-driven multi-agent framework that converts implicit interface assumptions into explicit, machine-checkable contracts and returns tool-generated diagnostics to the agent responsible for the affected module. Four specialized agents handle architecture specification, control logic, datapath integration, and verification. A single-cycle RISC-V processor integrating a predefined Intellectual Property (IP) core for 32-bit signed combinational multiplication serves as a controlled benchmark task for evaluating multi-module generation, localized error correction, and differences among LLM backends. The framework addresses the gap between isolated code generation and executable processor-level verification by exposing structural assumptions early enough to support bounded regeneration of individual modules. Methods V-Agent receives a hierarchical JavaScript Object Notation (JSON) configuration specifying the selected LLM backend, generation and retry parameters, architectural attributes, task operations, data widths, and test cases. The Architect Agent generates the top-level ports, control signals, datapath components, and opcode mappings. The Control Unit Agent produces synthesizable instruction-decoding and control logic. The Datapath Agent generates arithmetic, register-file, program-counter, routing, and top-level integration logic and instantiates the predefined multiplier IP core. The Verification Agent generates memory models, testbenches, Verilator drivers, and execution scripts. The processor and accelerator organization is shown in Fig. 1, and the multi-agent and verification feedback loops are summarized in Figs. 2 and 3. JSON interface contracts record port names, directions, widths, and types. A static analyzer parses the Verilog Abstract Syntax Tree (AST) and compares the generated port signatures with the corresponding contracts. Compilation and simulation provide additional diagnostics on syntax, connectivity, and functional behavior. When a check fails, the resulting diagnostic is returned to the responsible agent to trigger regeneration. The maximum number of retries is set to 3 (max_retries = 3). A fallback template is used only when repeated generation reaches the retry limit, allowing the remaining integration and verification steps to continue. The evaluated design supports two standard instructions and three experimental custom operations: MLOAD, PMUL, and PMAC. Six LLM backends, DeepSeek-V3, Claude Sonnet 4.5, Doubao-1.5 Pro, Gemini 1.5 Flash, Qwen3-235B, and GPT-5.1, are compared using module-compilation results, automatic-test performance, Code Quality Score, line-level code changes during manual repair, and Power, Performance, and Area (PPA) metrics from downstream implementation analysis. Fully automated results are recorded before manual modification, whereas Human-in-the-Loop (HITL) results are measured after localized repair. Results and Discussions The outputs of the monolithic, one-shot baseline fail system-level compilation because of context, interface, connection, or incomplete-state-logic problems. By contrast, the V-Agent pipeline produces designs that can proceed to system-level compilation (Table 4). This finding is limited to the present benchmark. In the fully automated evaluation, DeepSeek-V3 and Claude Sonnet 4.5 complete all five task operations, compile all eight RTL modules, and pass 70 of 78 automatic tests (Table 6). Doubao-1.5 Pro and Gemini 1.5 Flash compile 6 of 8 modules, GPT-5.1 compiles 7 of 8, and Qwen3-235B compiles 4 of 8. The generated designs support different numbers of executable automatic tests. Therefore, the results retain the raw counts and denominators rather than treating all test totals as directly comparable. Figure 4 presents the task-operation completion and automatic-test pass ratios. An interface-width mismatch illustrates how the feedback mechanism supports localized correction. The Datapath Agent initially defines MemToReg as a one-bit signal, while the additional multiplier-result path requires a two-bit selector. The contract checker identifies the mismatch and returns the diagnostic to the responsible agent. The agent regenerates the affected module in approximately 15 s, after which compilation and testing pass (Table 7). In the complete case study, the four agents generate eight RTL modules and 17 verification files in about 5 min. All eight modules compile, and four system-level programs produce the expected final register states and waveforms. The generated arithmetic execution and writeback path is shown in Fig. 5. After localized HITL edits, all six designs compile all eight RTL modules and pass the same set of 78 tests. The average line-level code-change rate is 4.37%, ranging from 1.3% to 9.5% (Table 9). PPA analysis shows that Claude Sonnet 4.5, DeepSeek-V3, and Gemini 1.5 Flash complete synthesis and timing analysis. GPT-5.1 completes gate-level mapping, but its timing analysis fails to converge because of a combinational loop. The unusually small implementations produced by Doubao-1.5 Pro and Qwen3-235B exhibit large-scale logic pruning during synthesis (Table 8). Among 126 classified errors at the generation and compilation stages, 54 are Verilog semantic errors, 36 are interface-width errors, 26 are cascading failures, and 10 are custom-operation semantic errors (Table 10). Conclusions V-Agent structures processor RTL generation as a coordinated workflow among specialized agents connected by explicit interface contracts and tool feedback. The evaluated RISC-V arithmetic-IP task shows that structural interface mismatches can be localized and corrected without regenerating the entire design. HITL results further distinguish initial generation quality from engineering repairability. The principal contribution is a coordination mechanism that converts cross-module assumptions into machine-checkable contracts and returns AST, compilation, and simulation diagnostics to the responsible agent. The framework complements existing synthesis, simulation, high-level synthesis, and verification tools rather than replacing them. The evidence is limited to a single-cycle RISC-V core, a predefined 32-bit multiplier IP core, task configurations containing 5–15 operations, and nonuniform executable test workloads. Verilator cannot expose every timing defect, and the PPA study requires more complete activity information, supply conditions, and netlist checks. Future work will extend the workflow to pipelined processors and coverage-guided automated repair.
- Multi-Agent systems,
- Large language models,
- RISC-V,
- Arithmetic IP integration

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