A Method for Parallel Testing of Interlayer Vias in Monolithic 3D Integrated Circuits

CHEN Tian; CHEN Weikun; LIU Jun; LIANG Huaguo; LU Yingchun

doi:10.11999/JEIT251375

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CHEN Tian, CHEN Weikun, LIU Jun, LIANG Huaguo, LU Yingchun. A Method for Parallel Testing of Interlayer Vias in Monolithic 3D Integrated Circuits[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251375

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CHEN Tian, CHEN Weikun, LIU Jun, LIANG Huaguo, LU Yingchun. A Method for Parallel Testing of Interlayer Vias in Monolithic 3D Integrated Circuits[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251375

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A Method for Parallel Testing of Interlayer Vias in Monolithic 3D Integrated Circuits

doi: 10.11999/JEIT251375 cstr: 32379.14.JEIT251375

1.
School of Computer Science and Information Engineering, Hefei University of Technology, Hefei 230601, China
2.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: The National Natural Science Foundation of China (62174048, 62027815)

Received Date: 2025-12-30
Accepted Date: 2026-02-10
Rev Recd Date: 2026-02-10

Available Online: 2026-03-04

Abstract

Abstract

Objective As device dimensions in conventional two-dimensional integrated circuits approach fundamental physical limits, further improvements in performance and integration density face significant challenges. Monolithic three-dimensional integrated circuits (M3D ICs), which sequentially stack multiple active device layers on a single wafer, provide an effective solution to overcome these limitations. In M3D ICs, monolithic inter-tier vias (MIVs) are employed to realize vertical interconnections between device tiers. Compared with through-silicon vias (TSVs), MIVs feature much smaller dimensions, lower parasitic capacitance, and shorter interconnect delay. However, their small electrical variations and massive quantity cause defects to manifest mainly as subtle delay shifts, posing stringent requirements on test accuracy, efficiency, and robustness against Process, Voltage, and Temperature (PVT) variations. Existing MIV testing approaches suffer from limited scalability, strong PVT sensitivity, and difficulty in simultaneously achieving small-delay defect detection and fault localization in large-scale arrays. To address these challenges, a parallel MIV testing method based on a time-to-digital converter (TDC) is presented to enable efficient and reliable testing of large MIV arrays with low area and time overhead. Methods Large-scale MIVs are logically organized into a two-dimensional array structure. Each basic test cell consists of a device-under-test MIV, a tri-state buffer, and a D flip-flop, and multiple cells are cascaded to form row test chains and column test chains. By systematically exploiting the inherent input capacitance mismatch between the data and clock terminals of the D flip-flop, an embedded TDC structure incorporating the MIV under test is constructed. Test stimuli are generated by a digitally controlled delay line (DCDL), which produces START and STOP pulse signals with multiplicatively adjustable phase differences and injects them into different propagation paths of the test chains, enabling time quantization through a signal chasing mechanism. Structural symmetry between the test chains is employed to mitigate the influence of PVT variations. As the START and STOP phase difference is progressively amplified, multiple TDC readings are collected to characterize defect-induced small delay variations and to distinguish them from measurement noise and PVT-induced fluctuations. After fault information is obtained for individual test chains, cross-analysis of row and column test results enables fault localization within the two-dimensional MIV array. Results and Discussions Simulation results based on the Nangate 45 nm standard cell library demonstrate that, under fault-free conditions, TDC readings obtained at different phase difference settings exhibit a stable linear proportional relationship (Fig. 7). Extensive Monte Carlo simulations are performed to determine a robust deviation tolerance threshold of 2, which effectively separates normal variations caused by PVT fluctuations from abnormal shifts induced by defects. Fault injection experiments verify that small delay defects occurring on both the START chain and the STOP chain can be effectively detected and distinguished (Fig. 8). In terms of quantitative detection capability, the minimum detectable resistive open defect is approximately 8.4 kΩ, while the maximum detectable leakage defect and resistive short defect are about 67 kΩ and 32 kΩ, respectively, outperforming existing methods (Fig. 9). Moreover, the row–column decomposition architecture effectively alleviates the growth of test time as the MIV array size increases, resulting in a substantial reduction in overall test overhead. Area evaluation indicates that the average area overhead of the embedded built-in self-test structure is only 5.594 µm² per MIV, making it suitable for high-density M3D integration. Conclusions A parallel TDC-based testing approach for large-scale MIV arrays is presented, which combines row–column decomposition, phase-difference multiplication, and proportional deviation-based decision mechanisms to achieve efficient detection and accurate localization of both hard faults and small delay defects. Structural symmetry within the test chains effectively enhances robustness against PVT variations. Simulation results confirm that the proposed method can reliably detect resistive open, leakage, and short defects while maintaining low area and time overhead. Compared with existing techniques, a favorable balance among test accuracy, PVT robustness, test efficiency, and hardware cost is achieved. Owing to its scalability and practical feasibility, the proposed approach provides an effective and reliable solution for MIV testing in advanced monolithic three-dimensional integrated circuits.
- Monolithic 3D Integrated Circuits (M3D ICs),
- Monolithic Inter-tier Via (MIV),
- Time-to-Digital Converter (TDC),
- Parallel test,
- Built-in self-test (BIST)

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References(20)

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