Design of an Aerospace-grade Radiation-hardened SRAM Cell for High-speed Read/Write Applications

CAI Shuo; SHUAI Wei; HU Xing; LIANG Xinjie; HUANG Zhu; YU Fei

doi:10.11999/JEIT251287

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CAI Shuo, SHUAI Wei, HU Xing, LIANG Xinjie, HUANG Zhu, YU Fei. Design of an Aerospace-grade Radiation-hardened SRAM Cell for High-speed Read/Write Applications[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251287

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CAI Shuo, SHUAI Wei, HU Xing, LIANG Xinjie, HUANG Zhu, YU Fei. Design of an Aerospace-grade Radiation-hardened SRAM Cell for High-speed Read/Write Applications[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251287

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Design of an Aerospace-grade Radiation-hardened SRAM Cell for High-speed Read/Write Applications

doi: 10.11999/JEIT251287 cstr: 32379.14.JEIT251287

1.
School of Physics and Electronic Science, Changsha University of Science & Technology, Changsha 410114, China
2.
Hunan Kangpu Communication Technology Co., Ltd., Changsha 410200, China

Funds: The National Natural Science Foundation of China (62172058)

Received Date: 2025-12-04
Accepted Date: 2026-03-03
Rev Recd Date: 2026-02-16

Available Online: 2026-03-15

Abstract

Abstract

Objective With the continued scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technology nodes and the reduction in supply voltage, Static Random Access Memory (SRAM) in aerospace environments becomes increasingly sensitive to high-energy particle radiation and is prone to Single-Node Upset (SNU) and Double-Node Upset (DNU). This sensitivity poses a serious challenge to the reliability of spaceborne Systems-on-Chip (SoC). Existing Radiation-Hardened-By-Design (RHBD) structures, however, usually cannot balance strong radiation tolerance with high-speed access performance. This work therefore aims to design an aerospace-grade radiation-hardened SRAM cell for high-speed read/write applications that provides both strong radiation resistance and fast access performance. Methods The proposed Read Fast and Write Fast 16-Transistor (RFWF16T) SRAM is built on a dual-source isolation architecture composed of 16 transistors (8 PMOS and 8 NMOS) (Fig. 1, Fig. 2). By using a symmetric recovery mechanism, the RFWF16T reduces the number of key sensitive nodes to only two. Redundant transistors (P2 and P6) are used to establish a stable high-level isolation state, which isolates the storage nodes from potential disturbances during the non-access phase. To achieve high-speed operation, the RFWF16T combines a short feedback path with a low-impedance voltage discharge loop. Unlike conventional hardened cells that rely on stacked transistors, which increase resistance and delay, the RFWF16T adopts a parallel access topology connected to word lines and bit lines. This configuration forms a low-impedance path during write operations and significantly accelerates node voltage switching (Fig. 3). Performance verification confirms the self-recovery capability of the four data nodes. A comprehensive variation analysis is conducted, including Process-Voltage-Temperature (PVT) variations and 2,000-point Monte Carlo simulations. Additionally, an improved Electrical Quality Metric (EQM) is proposed to evaluate multidimensional performance quantitatively. Results and Discussions The RFWF16T exhibits strong overall performance, particularly in overcoming the speed bottleneck of hardened SRAM cells. In terms of access speed, the RFWF16T performs substantially better than typical models such as S8P8N, SAW16T, and RH20T. Under standard conditions (28 nm CMOS process, 1.0 V, 25 °C, TT corner), the RFWF16T achieves a Read Access Time (RAT) of 20.97 ps and a Write Access Time (WAT) of 2.72 ps. These values correspond to average speed improvements of 46.65% and 14.77%, respectively, over eight comparable hardened structures (Table 2). PVT analysis confirms that the RFWF16T maintains the lowest latency across voltages from 0.7 V to 1.1 V and temperatures from -25 °C to 125 °C (Fig. 6). This write-speed advantage is attributed to the removal of write contention through optimized discharge paths. In terms of noise margin and stability, the RFWF16T demonstrates strong robustness and achieves the highest Write Word-line Toggle Voltage (WWTV) among nine comparative structures. Its Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) also rank among the best, which ensures stability under disturbances (Fig. 7). In radiation hardening, the RFWF16T achieves a 100% self-recovery rate for SNUs and an 83.3% recovery rate for DNUs, reaching the state-of-the-art level among DNU-recoverable units (Table 1). Monte Carlo simulations confirm that the average recovery times of the internal nodes range from 1.09 ns to 1.19 ns (Fig. 4, Fig. 5). In terms of overhead, the RFWF16T maintains a normalized area of 1.00× (4.3 μm × 1.9 μm) (Table 3, Fig. 2) and an average power consumption of 23.45 nW (Table 4). Although the power consumption is slightly higher, this increase is a reasonable trade-off for the substantial speed advantage. In the EQM evaluation, the RFWF16T obtains the highest score, which confirms its overall advantage in balancing reliability, speed, and stability (Fig. 7). Conclusions A radiation-hardened SRAM cell, RFWF16T, is proposed for aerospace-grade high-speed read/write applications. The cell contains only two sensitive nodes and achieves 100% self-recovery for SNUs and an 83.3% recovery rate for DNUs, which demonstrates strong radiation tolerance. Compared with eight other SRAM cells, the RFWF16T significantly reduces read and write delay with only a slight increase in area and power consumption, while maintaining good noise immunity and the best electrical quality metric. PVT and Monte Carlo simulations further confirm the stability and robustness of the proposed cell under different operating conditions. Future work will focus on array-level integration and tape-out verification, and on its application in satellite-borne high-speed data processing.
- Static Random Access Memory (SRAM),
- Radiation hardening,
- Single Node Upset (SNU),
- Double Node Upset (DNU),
- High-speed read/write access

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References(24)

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