A Testability Evaluation Method Based on Reconvergent Fan-out

WU Wenjun; LIANG Huaguo; YOU Chang; DOU Xianrui; XIAO Jiahui; LU Yingchun

doi:10.11999/JEIT251286

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WU Wenjun, LIANG Huaguo, YOU Chang, DOU Xianrui, XIAO Jiahui, LU Yingchun. A Testability Evaluation Method Based on Reconvergent Fan-out[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251286

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WU Wenjun, LIANG Huaguo, YOU Chang, DOU Xianrui, XIAO Jiahui, LU Yingchun. A Testability Evaluation Method Based on Reconvergent Fan-out[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251286

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A Testability Evaluation Method Based on Reconvergent Fan-out

doi: 10.11999/JEIT251286 cstr: 32379.14.JEIT251286

School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: The National Major Research Instrument Development Project (62027815), The National Natural Science Foundation of China Key Project (62174048, 62274052)

Received Date: 2025-12-03
Accepted Date: 2026-03-09
Rev Recd Date: 2026-03-09

Available Online: 2026-03-22

Abstract

Abstract

Objective As the scale and structural complexity of integrated circuits continue to increase, accurate testability evaluation has become essential for Trojan detection, fault diagnosis, and test-point optimization in modern Design-For-Testability (DFT) flows. Metrics such as controllability, observability, and fault coverage rely heavily on reliable probabilistic modeling of signal propagation. However, existing analytical and learning-based approaches often exhibit degraded accuracy in circuits containing dense Reconvergent Fan-Out (RFO) structures, where strong signal correlation invalidates classical independence assumptions and introduces significant estimation bias. Although several enhanced techniques attempt to incorporate structural information, many suffer from high computational cost or limited scalability when applied to deeper or more reconvergent logic networks. This work aims to address these limitations by proposing a testability evaluation method that incorporates RFO structural characteristics to improve modeling accuracy while maintaining practical computational efficiency. Methods The proposed approach begins with a structural-analysis algorithm that identifies RFO regions through a topological traversal of the circuit. A dedicated RFO-recognition mechanism maps each root fan-out node to its corresponding reconvergent fan-out nodes, capturing the structural dependencies that govern correlated signal behavior and providing the foundation needed for accurate probabilistic modeling. Building on this structural extraction, a weighted conditional-probability model is formulated to correct testability distortion within reconvergent regions. Unlike prior optimization schemes, the weighting strategy assigns influence-based weights derived from the contribution of each root node to the target node, yielding probability estimates that better reflect real testability behavior. Furthermore, an efficient computational framework is developed, integrating conditional probability propagation and weight selection within a single topological-traversal process, thereby maintaining low algorithmic complexity while enhancing accuracy. Results and Discussions The proposed method is evaluated on representative benchmark circuits from the ISCAS-85, ISCAS-89, ITC’99 , and EPFL suites. Performance is assessed in terms of controllability accuracy, ordering consistency, fault-coverage estimation, and runtime efficiency. For controllability prediction, the method achieves an average RMSE of 0.0568, corresponding to an average reduction of 25% compared with existing techniques, as reported in Table 2. Ordering consistency also improves, with the average Spearman correlation coefficient reaching 0.935, outperforming existing techniques. Fault-coverage estimation demonstrates similarly strong performance, with an average relative error of 3.64%, which is lower than previously reported methods, as shown in Table 1. Runtime analysis further indicates that the proposed framework maintains practical computational efficiency. Across all benchmark circuits, the method achieves an average speedup of 7× while preserving high accuracy, as illustrated in Figure 5. Conclusions This work addresses the degra dation of testability-evaluation accuracy caused by reconvergent fan-out structures in integrated circuits by proposing a reconvergent-fan-out-aware testability analysis method. The presented RFO-structure identification algorithm extracts reconvergent information at the topology level and establishes explicit mappings between root nodes and reconvergent fan-out nodes. Based on this structural foundation, a weighted conditional-probability model is constructed to mitigate probability distortion induced by signal correlation in RFO regions. An efficient computational framework is further developed to integrate the entire computation within a streamlined traversal-based process. Experimental results demonstrate that the proposed technique achieves accurate fitting of controllability RMSE and ordering consistency with respect to simulation-based ground truth. In testability estimation, the predicted fault-coverage values also match simulation results closely. While maintaining high accuracy, it also exhibits low computational overhead.
- Testability Measurement,
- Reconvergent Fan-out,
- Fault Coverage,
- Controllability/Observability Procedure (COP)

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References(18)

References

[1]	WANG L T, WU Chengwen, and WEN Xiaoqing. VLSI Test Principles and Architectures: Design for Testability[M]. San Francisco: Morgan Kaufmann Publishers, 2006: 1–34.
[2]	POMERANZ I. Diagnostic test point insertion and test compaction[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(2): 276–285. doi: 10.1109/TVLSI.2022.3218924.
[3]	KIM J, KIM H, PARK J, et al. A new test point insertion using weight adjusted grouping[J]. IEEE Access, 2025, 13: 95934–95944. doi: 10.1109/ACCESS.2025.3575800.
[4]	GOLDSTEIN L H and THIGPEN E L. SCOAP: Sandia controllability/observability analysis program[C]. Proceedings of the 17th Design Automation Conference, Minneapolis, USA, 1980: 190–196. doi: 10.1145/800139.804528.
[5]	BRGLEZ F. On testability analysis of combinational networks[J]. IEEE International Symposium on Circuits and Systems, 1984, 1: 221–225.
[6]	SCHLITT L, AGNIHOTRI P, KALLA P, et al. Silicon photonic test-point selection by integrating design parameters with hypergraph partitioning[C]. Proceedings of 2025 IEEE International Test Conference, San Diego, USA, 2025: 262–271. doi: 10.1109/ITC58126.2025.00033.
[7]	CHANG A C C, HUANG R H M, and WEN C H P. CASSER: A closed-form analysis framework for statistical soft error rate[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21(10): 1837–1848. doi: 10.1109/TVLSI.2012.2220386.
[8]	CHEN Liang, EBRAHIMI M, and TAHOORI M B. CEP: Correlated error propagation for hierarchical soft error analysis[J]. Journal of Electronic Testing, 2013, 29(2): 143–158. doi: 10.1007/s10836-013-5365-0.
[9]	CHEN Chunhong and ZHAN Suoyue. A hybrid method for signal probability estimation with combinational circuits[C]. Proceedings of 2022 IEEE Asia Pacific Conference on Circuits and Systems, Shenzhen, China, 2022: 472–475. doi: 10.1109/APCCAS55924.2022.10090301.
[10]	JAHANIRAD H. CC-SPRA: Correlation coefficients approach for signal probability-based reliability analysis[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(4): 927–939. doi: 10.1109/TVLSI.2018.2886027.
[11]	WU Nan, LI Yingjie, YANG Hang, et al. Survey of machine learning for software-assisted hardware design verification: Past, present, and prospect[J]. ACM Transactions on Design Automation of Electronic Systems, 2024, 29(4): 59. doi: 10.1145/3661308.
[12]	IMMANUEL J and MILLICAN S K. Calculating signal controllability using neural networks: Improvements to testability analysis and test point insertion[C]. Proceedings of the 2020 IEEE 29th North Atlantic Test Workshop, Albany, USA, 2020: 1–6. doi: 10.1109/NATW49237.2020.9153082.
[13]	LI Min, KHAN S, SHI Zhengyuan, et al. DeepGate: Learning neural representations of logic gates[C]. Proceedings of the 59th ACM/IEEE Design Automation Conference, San Francisco, USA, 2022: 667–672. doi: 10.1145/3489517.3530497.
[14]	CHAO Zhiteng, SUN Bin, LYU Hongqin, et al. HighTPI: A hierarchical graph based intelligent method for test point insertion[C]. Proceedings of the 2025 IEEE 43rd VLSI Test Symposium, Tempe, USA, 2025: 1–7. doi: 10.1109/VTS65138.2025.11022820.
[15]	DAS N, PAULS F, HASLER M, et al. A survey on recent developments in SCOAP-based hardware Trojan detection strategies[C]. Proceedings of 2025 IEEE International Symposium on Circuits and Systems, London, United Kingdom, 2025: 1–5. doi: 10.1109/ISCAS56072.2025.11043879.
[16]	RAKESH M B, DAS P, SAI PRANAV K R, et al. GRIPT: Graph attention-assisted inductive methodology for fast and accurate average power estimation from RTL simulation skipping gate-level simulation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, 44(11): 4209–4221. doi: 10.1109/TCAD.2025.3563420.
[17]	PARIA S, GAIKWAD P, DASGUPTA A, et al. LATENT: Leveraging automated test pattern generation for hardware Trojan detection[C]. Proceedings of the 2024 IEEE 33rd Asian Test Symposium, Ahmedabad, India, 2024: 1–6. doi: 10.1109/ATS64447.2024.10915238.
[18]	ABRAMOVICI M, BREUER M A, and FRIEDMAN A D. Digital Systems Testing and Testable Design[M]. Beijing: Tsinghua University Press, 2004: 1–36.