A Lightweight and High-Reliability Challenge Generation Strategy for APUF

LAN Guohao; ZHANG Hui; DUO Bin; WANG Zibin; ZHOU Rang; LI Dongfen

doi:10.11999/JEIT251073

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2026 >

LAN Guohao, ZHANG Hui, DUO Bin, WANG Zibin, ZHOU Rang, LI Dongfen. A Lightweight and High-Reliability Challenge Generation Strategy for APUF[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251073

Citation:

LAN Guohao, ZHANG Hui, DUO Bin, WANG Zibin, ZHOU Rang, LI Dongfen. A Lightweight and High-Reliability Challenge Generation Strategy for APUF[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251073

Citation:

PDF( 895 KB)

A Lightweight and High-Reliability Challenge Generation Strategy for APUF

doi: 10.11999/JEIT251073 cstr: 32379.14.JEIT251073

1.
School of Computer and Network Security, Chengdu University of Technology, Chengdu 610059, China
2.
Key Laboratory of Information System Security Technology, Beijing 100093, China

Funds: Higher Education Talent Training Quality and Teaching Reform Project (JG2420017, JG2430165)

Received Date: 2025-10-11
Accepted Date: 2026-03-18
Rev Recd Date: 2026-03-17

Available Online: 2026-04-06

Abstract

Abstract

Objective The Arbiter Physical Unclonable Function (APUF) is a lightweight security primitive that has been widely adopted in identity authentication and key generation for resource-constrained devices. However, its response consistency is highly sensitive to environmental perturbations, leading to inconsistent responses for the same challenge under different conditions, severely undermining the reliability of APUF-based security systems. Existing reliability improvement schemes for APUF, which mainly rely on hardware modification or challenge screening, generally suffer from high resource overhead and low efficiency. To address the limitations of these existing solutions, a Delay-Constrained Challenge Generation Strategy (DCGS) is proposed to enhance APUF reliability without extra hardware overhead or screening-related inefficiencies. Methods The core of DCGS lies in modeling APUF path delay properties and constructing challenges with constrained delay differences to ensure response stability. First, a logistic regression (LR) model is established to characterize the relationship between APUF challenge bits and path delays. From the trained LR model, a delay weight vector is derived to quantify the contribution of each challenge bit to the overall path delay. Second, a two-stage challenge generation mechanism is designed to integrate delay constraint control: The first stage is prefix bit initialization, which generates distinct prefix sequences to establish a stable delay baseline for subsequent bit extension. The second stage is bit-wise extension, where each remaining challenge bit is dynamically determined based on the delay weight vector. During this extension process, the cumulative delay difference of the challenge is monitored in real time, ensuring it stays within a preset threshold range. Unlike traditional screening methods that post-process candidate challenges, DCGS directly generates stable challenges by design, eliminating the need for candidate pools and improving generation efficiency. Results and Discussions Performance evaluations of DCGS are conducted under varying noise intensities. At a noise intensity of 0.3 (maximum practical level), the reliability of DCGS-generated challenges remains at 100% (Fig.2). In terms of generation efficiency, DCGS consumes only 0.017 seconds to generate 10,000 challenges (Table 4). For response uniformity, DCGS achieves a value of 50.02% (Table 4). For uniqueness, it reaches 50.46% (Table 4). These two key metrics are both close to the ideal theoretical value of 50%. Security analysis shows that the average bit entropy of DCGS-generated challenges is 0.9807 (Fig.3), and the conditional entropy is 0.9878—only 0.0023 lower than that of random challenges (0.9901). Conclusions This paper proposes a delay-constrained challenge generation strategy for APUF, aiming to address the problems of inconsistent responses, low generation efficiency, and high hardware resource consumption of traditional schemes in high-noise environments. By modeling the path delay characteristics of APUF using LR and integrating a prefix initialization mechanism with a bit-wise extension mechanism, the strategy ensures that the generated challenges meet the preset delay difference threshold range. Through this method, the DCGS achieves high reliability, high efficiency, and good response uniformity without increasing hardware overhead. Experimental results show that DCGS can effectively enhance the reliability of APUF in complex environments, providing strong technical support for secure applications in resource-constrained devices.
- Arbiter physical unclonable function,
- Reliability improvement,
- Machine learning,
- Generation strategy

FullText(HTML)

References(22)

References

[1]	HERDER C, YU M D, KOUSHANFAR F, et al. Physical unclonable functions and applications: A tutorial[J]. Proceedings of the IEEE, 2014, 102(8): 1126–1141. doi: 10.1109/JPROC.2014.2320516.
[2]	HEMAVATHY S and BHAASKARAN V S K. Arbiter PUF—a review of design, composition, and security aspects[J]. IEEE Access, 2023, 11: 33979–34004. doi: 10.1109/ACCESS.2023.3264016.
[3]	KANSAL M, ROY A, ROY D, et al. Priority arbiter PUF: Analysis[J]. Discrete Applied Mathematics, 2024, 356: 71–95. doi: 10.1016/j.dam.2024.05.013.
[4]	WANG Yao, ZHANG Guangyang, MEI Xue, et al. A high-reliability, non-CRP-discard arbiter PUF based on delay difference quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, 72(2): 573–585. doi: 10.1109/TCSI.2024.3466972.
[5]	DELVAUX J, GU Dawu, SCHELLEKENS D, et al. Helper data algorithms for PUF-based key generation: Overview and analysis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(6): 889–902. doi: 10.1109/TCAD.2014.2370531.
[6]	张源, 罗静茹, 张吉良. SDL PUF: 高可靠自适应偏差锁定PUF电路[J]. 电子与信息学报, 2024, 46(5): 2274–2280. doi: 10.11999/JEIT231313. ZHANG Yuan, LUO Jingru, and ZHANG Jiliang. SDL PUF: A high reliability self-adaption deviation locking PUF[J]. Journal of Electronics & Information Technology, 2024, 46(5): 2274–2280. doi: 10.11999/JEIT231313.
[7]	徐梦凡, 张跃军, 刘天翔, 等. 基于自检测修复的比特配置物理不可克隆函数电路设计[J]. 电子与信息学报, 2025, 47(9): 3292–3302. doi: 10.11999/JEIT250359. XU Mengfan, ZHANG Yuejun, LIU Tianxiang, et al. Bit-configurable physical unclonable function circuit based on self-detection and repair method[J]. Journal of Electronics & Information Technology, 2025, 47(9): 3292–3302. doi: 10.11999/JEIT250359.
[8]	WEN Yuejiang and LAO Yingjie. Enhancing PUF reliability by machine learning[C]. 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, USA, 2017: 1–4. doi: 10.1109/ISCAS.2017.8050672.
[9]	ZHOU Ziyu, WANG Pengjun, LI Gang, et al. Improving the stability of APUF to 100% without extra hardware overhead for enhancing the performance of security authentication protocols[J]. IEEE Internet of Things Journal, 2025, 12(12): 19818–19832. doi: 10.1109/JIOT.2025.3541434.
[10]	MA Chaofang, MU Jianan, YE Jing, et al. Online reliability evaluation design: Select reliable CRPs for arbiter PUF and its variants[C]. 2023 IEEE European Test Symposium (ETS), Venezia, Italy, 2023: 1–6. doi: 10.1109/ETS56758.2023.10174198.
[11]	BANSAL G and SIKDAR B. Achieving secure and reliable UAV authentication: A Shamir’s secret sharing based approach[J]. IEEE Transactions on Network Science and Engineering, 2024, 11(4): 3598–3610. doi: 10.1109/TNSE.2024.3381599.
[12]	MILLWOOD O, MISKELLY J, YANG Bohao, et al. PUF-phenotype: A robust and noise-resilient approach to aid group-based authentication with DRAM-PUFs using machine learning[J]. IEEE Transactions on Information Forensics and Security, 2023, 18: 2451–2465. doi: 10.1109/TIFS.2023.3266624.
[13]	姜冬梅, 唐旭升, 李冰, 等. 针对静态随机存取存储器物理不可克隆功能密钥提取的优化方法研究[J]. 电子与信息学报, 2025, 47(9): 3220–3229. doi: 10.11999/JEIT250551. JIANG Dongmei, TANG Xusheng, LI Bing, et al. Research on optimization methods for static random-access memory-physical unclonable function key extraction[J]. Journal of Electronics & Information Technology, 2025, 47(9): 3220–3229. doi: 10.11999/JEIT250551.
[14]	RÜHRMAIR U and SÖLTER J. PUF modeling attacks: An introduction and overview[C]. 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2014: 1–6. doi: 10.7873/DATE.2014.361.
[15]	LIM D, LEE J W, GASSEND B, et al. Extracting secret keys from integrated circuits[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(10): 1200–1205. doi: 10.1109/TVLSI.2005.859470.
[16]	KOYILY A, AVVARU S V S, ZHOU Chen, et al. Effect of aging on linear and nonlinear MUX PUFs by statistical modeling[C]. 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju, Korea (South), 2018: 76–83. doi: 10.1109/ASPDAC.2018.8297286.
[17]	MAES R. An accurate probabilistic reliability model for silicon PUFs[C]. Proceedings of 15th International Workshop on Cryptographic Hardware and Embedded Systems -- CHES 2013, Santa Barbara, USA, 2013: 73–89. doi: 10.1007/978-3-642-40349-1_5.
[18]	XU Chongyao, ZHANG Litao, MAK P I, et al. Fully symmetrical obfuscated interconnection and Weak-PUF-assisted challenge obfuscation strong PUFs against machine-learning modeling attacks[J]. IEEE Transactions on Information Forensics and Security, 2024, 19: 3927–3942. doi: 10.1109/TIFS.2024.3372801.
[19]	PAHLEVI R R, HASEGAWA H, YAMAGUCHI Y, et al. A pre-selection–enhanced arbiter PUF for strengthening PUF-based authentication[J]. IEEE Access, 2025, 13: 127526–127544. doi: 10.1109/ACCESS.2025.3590476.
[20]	GU Hongxiang, XU Teng, and POTKONJAK M. A low-power APUF-based environmental abnormality detection framework[C]. 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Taipei, China, 2017: 1–6. doi: 10.1109/ISLPED.2017.8009194.
[21]	KATZENBEISSER S, KOCABAŞ Ü, ROŽIĆ V, et al. PUFs: Myth, fact or busted? A security evaluation of physically unclonable functions (PUFs) cast in silicon[C]. Proceedings of 14th International Workshop on Cryptographic Hardware and Embedded Systems -- CHES 2012, Leuven, Belgium, 2012: 283–301. doi: 10.1007/978-3-642-33027-8_17.
[22]	GU Chongyan, LIU Weiqiang, CUI Yijun, et al. A flip-flop based arbiter physical unclonable function (APUF) design with high entropy and uniqueness for FPGA implementation[J]. IEEE Transactions on Emerging Topics in Computing, 2021, 9(4): 1853–1866. doi: 10.1109/TETC.2019.2935465.