Design of a Timing-Controlled Non-Volatile Flip-Flop with Low-Switching-Ratio FeFET

DU Shimin; YANG Chang; WANG Lunyao; ZHANG Zhe

doi:10.11999/JEIT251059

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DU Shimin, YANG Chang, WANG Lunyao, ZHANG Zhe. Design of a Timing-Controlled Non-Volatile Flip-Flop with Low-Switching-Ratio FeFET[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251059

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DU Shimin, YANG Chang, WANG Lunyao, ZHANG Zhe. Design of a Timing-Controlled Non-Volatile Flip-Flop with Low-Switching-Ratio FeFET[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT251059

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Design of a Timing-Controlled Non-Volatile Flip-Flop with Low-Switching-Ratio FeFET

doi: 10.11999/JEIT251059 cstr: 32379.14.JEIT251059

DU Shimin^{1, 2
,
,},
YANG Chang^{1, 2},
WANG Lunyao²,
ZHANG Zhe^{1, 2}

1.
College of Science & Technology Ningbo University, Ningbo 315300, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: National Natural Science Foundation of China (U23A20351, 62304115), Natural Science Foundation of Zhejiang Province (LDT23F04021F04), Open Project of Ningbo Key Laboratory of Intelligent Home Appliances (20250621)

Received Date: 2025-10-09
Accepted Date: 2026-05-15
Rev Recd Date: 2026-05-15

Available Online: 2026-06-03

Abstract

Abstract

Objective Nonvolatile processors(NVPs) have become a key technology for Internet-of-Things (IoT) and energy-harvesting systems, where maintaining computational states during unexpected power interruptions is essential. Conventional volatile processors rely on external nonvolatile memory(NVM) for state retention; however, this approach incurs significant latency and energy overheads. Integrated nonvolatile flip-flops using ferroelectric field-effect transistors(FeFETs) offer a promising alternative by enabling on-chip state backup and recovery. Nevertheless, existing single-ended FeFET-based flip-flops are prone to contention-induced failures during power-up recovery, especially when the FeFET on/off ratio degrades. This issue originates from competing discharge paths that lead to uncertainty in internal node voltage settling, thereby resulting in unreliable state restoration. To address this challenge, this work proposes a novel flip-flop architecture that replaces contention-based recovery with a timing-controlled two-phase mechanism. The primary objectives of this design are to achieve high-reliability recovery even under degraded FeFET on/off ratios as low as 10², optimize timing parameters such as Hold-Time and Clock-to-Q delay, and maintain low energy consumption suitable for IoT applications. Methods The proposed design is an extension of the Static Contention-Free Single-Phase-Clocked Flip-Flop(SSCFF), which inherently eliminates internal node contention through its fully static structure. Based on this foundation, one FeFET device and five additional MOSFETs are integrated to construct a single-ended nonvolatile flip-flop(NVFF). Two control signals, RES and MOD, are introduced to manage the recovery process.In the normal operation mode where MOD=0, the circuit functions as a conventional SSCFF and supports state backup during runtime. In the recovery mode where MOD=1, the recovery operation is divided into two distinct phases.In the pre-charge phase, when RES=0, the internal nodes are pre-charged to VDD. In the selective discharge phase, as RES transitions from low to high, the resistance state of the FeFET determines whether discharge occurs. If the FeFET is in the low-resistance state(LRS), a discharge path is formed, pulling the node voltage down to ground. If the FeFET remains in the high-resistance state(HRS), the node retains its charge until the next clock edge.This sequence of pre-charging followed by selective discharge eliminates contention during recovery and ensures that the internal node voltages settle deterministically and reliably.The design is implemented in a 130nm CMOS process with integrated FeFET models. Simulations, including Monte Carlo analysis, were performed in Cadence Virtuoso across a supply voltage range of 0.6–0.9 V and FeFET on/off ratios ranging from 10² to 10⁴. Key performance metrics, such as Setup-Time, Hold-Time, Clock-to-Q delay, restore energy, and recovery success rate, were evaluated and compared against traditional Transmission Gate Flip-Flop. Results and Discussions Simulation results show that the timing-controlled recovery improves reliability even under severe FeFET degradation. The proposed flip-flop achieves 100 % restore yield when the FeFET on/off ratio drops to 10². This is because the proposed structure eliminates the competing discharge paths. Timing metrics are also improved: the 3σ worst-case Hold-Time is reduced by 64.6 % , and the Clock-to-Q delay is shortened by 33.9 %. Although Setup-Time increases slightly, it can be compensated by device sizing. Restore energy remains in the low-fJ (10^–15 J) range across all supply voltages, rising only modestly compared with the TGFF because of the added pre-charge phase. Conclusions A Ferroelectric FET Nonvolatile Flip-Flop with timing-controlled two-phase recovery has been presented, addressing the contention-induced failure modes that limit low-voltage NVFF reliability. By integrating a single FeFET with an enhanced SSCFF structure and using RES signal to manage the pre-charge and discharge steps, high restore yield is maintained even under severely degraded FeFET on/off ratios, while Hold-Time and Clock-to-Q delay are significantly improved relative to traditional transmission-gate NVFFs. The proposed architecture offers a compelling solution for energy-constrained IoT processors requiring fast, reliable state preservation under unpredictable power conditions.

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