Design of a Timing-Controlled Nonvolatile Flip-Flop for Low-ON/OFF-Current-Ratio FeFETs

DU Shimin; YANG Chang; WANG Lunyao; ZHANG Zhe

doi:10.11999/JEIT251059

Volume 48 Issue 7

Jul. 2026

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Article Navigation > Journal of Electronics & Information Technology > 2026 > 48(7): 3181-3192

DU Shimin, YANG Chang, WANG Lunyao, ZHANG Zhe. Design of a Timing-Controlled Nonvolatile Flip-Flop for Low-ON/OFF-Current-Ratio FeFETs[J]. Journal of Electronics & Information Technology, 2026, 48(7): 3181-3192. doi: 10.11999/JEIT251059

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DU Shimin, YANG Chang, WANG Lunyao, ZHANG Zhe. Design of a Timing-Controlled Nonvolatile Flip-Flop for Low-ON/OFF-Current-Ratio FeFETs[J]. Journal of Electronics & Information Technology, 2026, 48(7): 3181-3192. doi: 10.11999/JEIT251059

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Design of a Timing-Controlled Nonvolatile Flip-Flop for Low-ON/OFF-Current-Ratio FeFETs

doi: 10.11999/JEIT251059 cstr: 32379.14.JEIT251059

DU Shimin^{1, 2
,
,},
YANG Chang^{1, 2},
WANG Lunyao²,
ZHANG Zhe^{1, 2}

1.
College of Science & Technology Ningbo, University, Ningbo 315300, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: The National Natural Science Foundation of China (U23A20351, 62304115), The Natural Science Foundation of Zhejiang Province (LDT23F04021F04), The Open Project of Ningbo Key Laboratory of Intelligent Home Appliances (20250621)

Received Date: 2025-10-09
Accepted Date: 2026-05-15
Rev Recd Date: 2026-05-15

Available Online: 2026-06-03

Publish Date: 2026-07-10

Abstract

Abstract

Objective Nonvolatile Processors (NVPs) are a key technology for Internet of Things (IoT) and energy-harvesting systems, in which computational states must be preserved during unexpected power loss. Conventional volatile processors rely on external Nonvolatile Memory (NVM) for state retention. However, this approach causes high latency and energy overhead. Integrated Nonvolatile Flip-Flops (NVFFs) based on Ferroelectric Field-Effect Transistors (FeFETs) provide a promising alternative by enabling on-chip state backup and recovery. However, existing single-ended FeFET-based flip-flops are prone to contention-induced recovery failures, especially when the FeFET ON/OFF current ratio degrades. This failure arises from contention among internal metal-oxide-semiconductor transistors, which makes internal node settling uncertain and causes unreliable state recovery. To address this issue, this paper proposes a timing-controlled NVFF architecture that replaces contention-based recovery with a two-stage recovery mechanism. The proposed design aims to achieve reliable recovery under degraded FeFET ON/OFF current ratios as low as 10², improve timing metrics such as hold time and clock-to-Q delay, and maintain low energy consumption for IoT applications. Methods The proposed design extends the Static Contention-Free Single-Phase-Clocked Flip-Flop (SSCFF), whose fully static structure suppresses internal node contention. On this basis, one FeFET and five additional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are integrated to construct a single-ended NVFF. Two control signals, RES and MOD, are used to manage the recovery process. In normal operation, MOD = 0, and the circuit functions as a conventional SSCFF while supporting runtime state backup. In recovery mode, MOD = 1, and the recovery process is divided into two stages. In the precharge stage, when RES = 0, the internal nodes are precharged to VDD. In the selective-discharge stage, RES switches from low to high, and the FeFET resistance state determines whether discharge occurs. If the FeFET is in the Low-Resistance State (LRS), a discharge path is formed, and the node voltage is pulled down to ground. If the FeFET is in the High-Resistance State (HRS), the node retains its charge until the next clock edge. This precharge-selective-discharge sequence removes recovery contention and enables deterministic internal node settling. The design is implemented using a 130 nm Complementary Metal-Oxide-Semiconductor (CMOS) process and an integrated FeFET model. Simulations are performed in Cadence Virtuoso across a supply voltage range of 0.6～0.9 V and FeFET ON/OFF current ratios from 10² to 10⁴. Key metrics, including setup time, hold time, clock-to-Q delay, recovery energy, and recovery success rate, are evaluated and compared with those of a conventional Transmission-Gate Flip-Flop (TGFF). Results and Discussions Simulation results show that timing-controlled recovery improves reliability under severe FeFET degradation. At an FeFET ON/OFF current ratio of 10², the proposed flip-flop achieves a 100% recovery success rate in 2000 Monte Carlo simulations. This improvement is attributed to the removal of contention among internal recovery paths. Timing metrics are also improved. The 3σ worst-case hold time is reduced by 64.6%, and the clock-to-Q delay is reduced by 33.9%. Although setup time increases slightly, this increase can be mitigated through device sizing. Recovery energy remains at the fJ level, with values of approximately 10 fJ under the tested conditions. This energy is only slightly higher than that of the TGFF because of the added precharge stage. Conclusions An FeFET-based NVFF with timing-controlled two-stage recovery is presented to address the contention-induced failure modes that limit low-voltage recovery reliability. By integrating a single FeFET into an enhanced SSCFF structure and using the RES signal to control precharge and selective discharge, the proposed design maintains a high recovery success rate even under severely degraded FeFET ON/OFF current ratios. It also improves hold time and clock-to-Q delay compared with conventional transmission-gate NVFFs. The proposed architecture provides an effective solution for energy-constrained IoT processors that require fast and reliable state preservation under unpredictable power conditions.

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References(28)

References

[1]	PORTAL S. Internet of Things (IoT) connected devices installed base worldwide from 2015 to 2025 (in Billions)[EB/OL]. https://www.statista.com/statistics/471264/iot-number-of-connected -devices-worldwide/, 2017.
[2]	KIM S, LIM S, KO D H, et al. Ferroelectric FET nonvolatile sense-amplifier-based flip-flops for low voltage operation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(1): 274–286. doi: 10.1109/TCSI.2023.3327294.
[3]	CHEN Yangyin. ReRAM: History, status, and future[J]. IEEE Transactions on Electron Devices, 2020, 67(4): 1420–1433. doi: 10.1109/TED.2019.2961505.
[4]	张立宁, 胡伟晨, 王新安, 等. 基于免疫算法的铁电场效应晶体管多态门设计方法[J]. 电子与信息学报, 2023, 45(9): 3157–3165. doi: 10.11999/JEIT230287. ZHANG Lining, HU Weichen, WANG Xin’an, et al. Design method of ferroelectric field effect transistor polymorphic gate based on immune algorithm[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3157–3165. doi: 10.11999/JEIT230287.
[5]	MEIHAR P, SRINU R, SARASWAT V, et al. FeFET-based MirrorBit cell for high-density NVM storage[J]. IEEE Transactions on Electron Devices, 2024, 71(4): 2380–2385. doi: 10.1109/TED.2024.3361843.
[6]	ZENG Binjian, LIAO Min, PENG Qiangxiang, et al. 2-Bit/cell operation of Hf_0.5Zr_0.5O₂ based FeFET memory devices for NAND applications[J]. IEEE Journal of the Electron Devices Society, 2019, 7: 551–556. doi: 10.1109/JEDS.2019.2913426.
[7]	蒋林, 张丁月, 李远成, 等. 基于忆阻器的1T1M可重构阵列结构[J]. 电子与信息学报, 2023, 45(8): 3047–3056. doi: 10.11999/JEIT220718. JIANG Lin, ZHANG Dingyue, LI Yuancheng, et al. 1T1M reconfigurable array structure based on memristor[J]. Journal of Electronics & Information Technology, 2023, 45(8): 3047–3056. doi: 10.11999/JEIT220718.
[8]	ALIPOUR KIASARA S and NIARAKI ASLI R. High efficiency nonvolatile D flip-flop[J]. Transactions on Machine Intelligence, 2023, 6(1): 41–52. doi: 10.47176/TMI.2023.41.
[9]	YAN Aibin, CHEN Yu, HUANG Zhengfeng, et al. A high-performance and P-type FeFET-based non-volatile latch[C]. 2023 IEEE 32nd Asian Test Symposium (ATS), Beijing, China, 2023: 1–5. doi: 10.1109/ATS59501.2023.10318017.
[10]	THIRUMALA S, RAHA A, GUPTA S, et al. Exploring the design of energy-efficient intermittently powered systems using reconfigurable ferroelectric transistors[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 30(4): 365–378. doi: 10.1109/TVLSI.2021.3125248.
[11]	SAKI A A, LIN S H, ALAM M, et al. A family of compact non-volatile flip-flops with ferroelectric FET[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(11): 4219–4229. doi: 10.1109/TCSI.2019.2927347.
[12]	ISHDORJ B and NA T. Spin-transfer-torque magnetic-tunnel-junction-based low-power nonvolatile flip-flop designs in the subthreshold voltage region[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(10): 1565–1577. doi: 10.1109/TVLSI.2023.3300032.
[13]	GONG Nanbo and MA T P. A study of endurance issues in HfO₂-based ferroelectric field effect transistors: Charge trapping and trap generation[J]. IEEE Electron Device Letters, 2018, 39(1): 15–18. doi: 10.1109/LED.2017.2776263.
[14]	TIAN Fengbin, ZHAO Shujing, XU Hao, et al. Impact of interlayer and ferroelectric materials on charge trapping during endurance fatigue of FeFET with TiN/Hf_xZr_1-xO₂/INterlayer/Si (MFIS) gate structure[J]. IEEE Transactions on Electron Devices, 2021, 68(11): 5872–5878. doi: 10.1109/TED.2021.3114663.
[15]	JERRY M, CHEN Paiyu, ZHANG Jianchi, et al. Ferroelectric FET analog synapse for acceleration of deep neural network training[C]. 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, 2017: 6.2. 1–6.2. 4. doi: 10.1109/IEDM.2017.8268338.
[16]	LI Xueqing, GEORGE S, LIANG Yuhua, et al. Lowering area overheads for FeFET-based energy-efficient nonvolatile flip-flops[J]. IEEE Transactions on Electron Devices, 2018, 65(6): 2670–2674. doi: 10.1109/TED.2018.2829348.
[17]	KIM Y, JUNG W, LEE I, et al. 27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications[C]. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, USA, 2014: 466–467. doi: 10.1109/ISSCC.2014.6757516.
[18]	YUAN Jiren and SVENSSON C. New single-clock CMOS latches and flipflops with improved speed and power savings[J]. IEEE Journal of Solid-State Circuits, 1997, 32(1): 62–69. doi: 10.1109/4.553179.
[19]	刘勇, 李泰昕, 祝希, 等. 基于铁电晶体管的存储与存算一体电路[J]. 电子与信息学报, 2023, 45(9): 3083–3097. doi: 10.11999/JEIT230370. LIU Yong, LI Taixin, ZHU Xi, et al. Memory and compute-in-memory based on ferroelectric field effect transistors[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3083–3097. doi: 10.11999/JEIT230370.
[20]	郭昕婕, 王光燿, 王绍迪. 存内计算芯片研究进展及应用[J]. 电子与信息学报, 2023, 45(5): 1888–1898. doi: 10.11999/JEIT220420. GUO Xinjie, WANG Guangyao, and WANG Shaodi. Technology developments and applications of in-memory computing processors[J]. Journal of Electronics & Information Technology, 2023, 45(5): 1888–1898. doi: 10.11999/JEIT220420.
[21]	吴乾火, 王伦耀, 查晓婧, 等. 可重构铁电数据选择器设计及在映射中的应用[J]. 电子与信息学报, 2025, 47(9): 3321–3332. doi: 10.11999/JEIT250263. WU Qianhuo, WANG Lunyao, ZHA Xiaojing, et al. Design of reconfigurable FeFET-MUX and its application in mapping[J]. Journal of Electronics & Information Technology, 2025, 47(9): 3321–3332. doi: 10.11999/JEIT250263.
[22]	RAFIQ M, CHAUHAN Y S, and SAHAY S. Compact XOR/XNOR-based adders and BNNs utilizing drain-erase scheme in ferroelectric FETs[J]. IEEE Journal of the Electron Devices Society, 2025, 13: 822–830. doi: 10.1109/JEDS.2024.3497147.
[23]	RAFIQ M, CHAUHAN Y S, and SAHAY S. Exploiting single ferroelectric FET for efficient implementation of majority gate function for approximate computing[C]. 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024: 1–3. doi: 10.1109/EDTM58488.2024.10511629.
[24]	QIN Laixiang, LI Chunlai, WEI Yiqun, et al. Recent developments in negative capacitance gate-all-around field effect transistors: A review[J]. IEEE Access, 2023, 11: 14028–14042. doi: 10.1109/ACCESS.2023.3243697.
[25]	SALAHUDDIN S and DATTA S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices[J]. Nano Letters, 2008, 8(2): 405–410. doi: 10.1021/nl071804g.
[26]	THIRUMALA S K, RAHA A, JAYAKUMAR H, et al. Dual mode ferroelectric transistor based non-volatile flip-flops for intermittently-powered systems[C]. The International Symposium on Low Power Electronics and Design, Seattle, USA, 2018: 31. doi: 10.1145/3218603.3218653.
[27]	LI Xueqing, GEORGE S, MA Kaisheng, et al. Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64(11): 2907–2919. doi: 10.1109/TCSI.2017.2702741.
[28]	WANG Yongbo, WANG Xiaohu, WAN Jiale, et al. RRAM-based NVFF: Harnessing AWT and differential power-up for enhanced power, speed, and reliability[J]. IEEE Transactions on Electron Devices, 2025, 72(7): 3593–3597. doi: 10.1109/TED.2025.3570994.