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HUI Zhanqiang, ZHANG Xinglong, HAN dongdong, LI Tiantian, GONG Jiamin. Inverse Design of a Silicon-Based Compact Polarization Splitter-Rotator[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250858
Citation: HUI Zhanqiang, ZHANG Xinglong, HAN dongdong, LI Tiantian, GONG Jiamin. Inverse Design of a Silicon-Based Compact Polarization Splitter-Rotator[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250858

Inverse Design of a Silicon-Based Compact Polarization Splitter-Rotator

doi: 10.11999/JEIT250858 cstr: 32379.14.JEIT250858
Funds:  National Key Research and Development Program Project (2022YFB2903201), Shaanxi Provincial Innovation Capacity Support Program Project (2022PT15)
  • Accepted Date: 2025-11-13
  • Rev Recd Date: 2025-11-13
  • Available Online: 2025-11-18
  •   Objective  The integrated polarization splitter-rotator (PSR), as one of the key photonic devices for manipulating the polarization state of light waves, has been widely used in various photonic integrated circuits (PICs). For PICs, device size becomes a major bottleneck limiting integration density. Compared to traditional design methods, which suffer from being time-consuming and producing larger device sizes, inverse design optimizes the best structural parameters of integrated photonic devices according to target performance parameters by employing specific optimization algorithms. This approach can significantly reduce device size while ensuring performance and is currently used to design various integrated photonic devices, such as wavelength/mode division multiplexers, all-optical logic gates, power splitters, etc. In this paper, the Momentum Optimization algorithm and the Adjoint Method are combined to inverse design a compact PSR. This can not only significantly improve the integration level of PICs but also offers a design approach for the miniaturization of other photonic devices.  Methods  First, based on a silicon-on-insulator (SOI) wafer with a thickness of 220 nm, the design region was discretized into 25×50 cylindrical elemental structures. Each structure has a radius of 50 nm and a height of 150 nm and is filled with an intermediate material possessing a relative permittivity of 6.55. Next, the adjoint method was employed for simulation to obtain gradient information over the design region. This gradient information was processed using the Momentum Optimization algorithm. Based on the processed gradient, the relative permittivity of each elemental structure was modified. During the optimization process, the momentum factor in the Momentum Optimization algorithm was dynamically adjusted according to the iteration number to accelerate the optimization. Meanwhile, a linear bias was introduced to artificially control the optimization direction of the relative permittivity. This bias gradually steered the permittivity values towards those of silicon and air as the iterations progressed. Upon completion of the optimization, the elemental structures were binarized based on their final relative permittivity values: structures with permittivity less than 6.55 were filled with air, while those greater than 6.55 were filled with silicon. At this stage, the design region consisted of multiple irregularly distributed air holes. To compensate for the performance loss incurred during binarization, the etching depth of air holes (whose pre-binarization permittivity was between 3 and 6.55) was optimized. Furthermore, adjacent air holes are merged to reduce manufacturing errors. This resulted in a final device structure composed of air holes with five distinct radii. Among these, three types of larger-radius air holes were selected. Their etching radii and depths were further optimized to compensate for the remaining performance loss. Finally, the device performance was evaluated through numerical analysis. Key parameters calculated include insertion loss (IL), crosstalk (CT), polarization extinction ratio (PER), and bandwidth. Additionally, tolerance analysis was performed to assess the robustness of the performance.  Results and Discussions   This paper presents the design of a compact PSR based on a 220-nm-thick SOI wafer, with dimensions of 5 µm in length and 2.5 µm in width. During the design process, the momentum factor within the Momentum Optimization algorithm was dynamically adjusted: a large momentum factor was selected in the initial optimization stages to leverage high momentum for accelerating escape from local maxima or plateau regions, while a smaller momentum factor was used in later stages to increase the weight of the current gradient. Compared to other optimization methods, the algorithm employed in this work required only 20%-33% of the iteration counts needed by other algorithms to achieve a Figure of Merit (FOM) value of 1.7, significantly enhancing optimization efficiency. Numerical analysis results demonstrate that this device achieves the following performance across the 1520-1575 nm wavelength band: low IL (TM0<1 dB,TE0<0.68 dB), low CT: (TM0<-23 dB, TE0<-25.2 dB), high PER: (TM0>17 dB, TE0>28.5 dB), process tolerance analysis indicates that the device exhibits robust fabrication tolerance. Within the 1520-1540 nm bandwidth, performance shows no significant degradation under variations of etching depth offset ±9 nm, etching radius offset ±5 nm. This demonstrates its excellent manufacturability robustness.  Conclusions   Through numerical analysis and comparison with devices designed in other literature, this work clearly demonstrates the feasibility of combining the adjoint method with the Momentum Optimization algorithm for designing the integrated PSR. Its design principle involves manipulating light propagation to achieve the polarization splitting and rotation effect by adjusting the relative permittivity to control the positions of the air holes. Compared to traditional design methods, inverse design enables the efficient utilization of the design region, thereby achieving a more compact structure. The PSR proposed in this work is not only significantly smaller in size but also exhibits larger fabrication tolerance. It holds significant potential for application in future large-scale PICs chips, while also offering valuable design insights for the miniaturization of other photonic devices.
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