Lightweight AdderNet Circuit Enabled by STT-MRAM In-Memory Absolute Difference Computation

WANG Lixun; ZHANG Yuejun; LI Qikang; ZHANG Huihong; WEN Liang

doi:10.11999/JEIT250627

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WANG Lixun, ZHANG Yuejun, LI Qikang, ZHANG Huihong, WEN Liang. Lightweight AdderNet Circuit Enabled by STT-MRAM In-Memory Absolute Difference Computation[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250627

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WANG Lixun, ZHANG Yuejun, LI Qikang, ZHANG Huihong, WEN Liang. Lightweight AdderNet Circuit Enabled by STT-MRAM In-Memory Absolute Difference Computation[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250627

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Lightweight AdderNet Circuit Enabled by STT-MRAM In-Memory Absolute Difference Computation

doi: 10.11999/JEIT250627 cstr: 32379.14.JEIT250627

1.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
2.
Department of Electronic Technology, China Coast Guard Academy, Ningbo 315801, China

Funds: The National Natural Science Foundation of China (62474100, 62174121, 62134002), “Vanguard Geese Leading and X” Science and Technology Program of Zhejiang Province (2025C01063), The Key R&D Program of Ningbo Science and Technology Yongjiang 2035 (2024Z139), The Key R&D Program of Cixi (CZ2025006), the Graduate Student Scientific Research and Innovation Project of Ningbo University

Received Date: 2025-04-28
Rev Recd Date: 2025-09-17

Available Online: 2025-09-19

Abstract

Abstract

Objective To address the challenges of complex multiply–accumulate operations and high energy consumption in hardware implementations of Convolutional Neural Networks (CNNs), this study proposes a Processing-In-Memory (PIM) AdderNet acceleration architecture based on Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), with innovations at the circuit level. Specifically, a novel in-situ absolute difference computation circuit is designed to support L1-norm operations, replacing traditional multipliers and simplifying the data path and computational logic. By leveraging magnetic resistance state mapping, a reconfigurable full-adder unit is developed that enables single-cycle carry-chain updates and multi-mode logic switching, thereby enhancing parallel computing efficiency and energy–performance ratio. Through array-level integration and coordinated control with heterogeneous peripheral circuits, this work establishes a scalable and energy-efficient PIM-based convolutional acceleration system, providing a practical and viable paradigm for deploying deep learning hardware in resource-constrained environments. Methods To achieve energy-efficient acceleration of AdderNet in resource-constrained environments, this study proposes a circuit-level Computing-In-Memory (CIM) architecture based on STT-MRAM. The L1 norm is embedded into the memory array to enable in-situ absolute difference computation, thereby replacing conventional multiply–accumulate operations and simplifying datapath complexity. To reduce redundant operations caused by frequent zero-value interactions in AdderNet, a sparsity-aware computation strategy is implemented, which bypasses invalid operations and lowers dynamic power consumption. A reconfigurable full-adder unit is further designed using magnetoresistive state mapping, supporting single-cycle carry-chain propagation and logic mode switching. These units are integrated into a scalable parallel array structure that performs L1-norm operations efficiently. The architecture is complemented by optimized dataflow control and heterogeneous peripheral circuits, forming a complete low-power AdderNet accelerator. Simulation and hardware-level validations confirm the accuracy, throughput, and energy efficiency of the proposed system under realistic workloads. Results and Discussions Simulation results confirm the effectiveness and efficiency of the proposed MRAM-based AdderNet hardware accelerator under realistic inference workloads. The fabricated full-adder unit supports in-memory computation with dual-mode configurability for both sum and carry operations (Fig. 2, Fig. 3). The proposed 1-bit full adder produces correct logical outputs in both modes, with timing waveforms validating reliable switching behavior under a 40 nm CMOS process (Fig. 7, Fig. 8). The parallel array structure, which integrates multiple MRAM-based full-adder units, enables efficient L1-norm-based convolution through element-wise absolute difference (Fig. 4) and maps standard convolution kernels into a format compatible with the proposed architecture (Fig. 5b). Device-level Monte Carlo simulations reveal tightly distributed resistance states, with coefficients of variation of low-resistance and high-resistance states of approximately 1.1% (CVLRS) and 1.2% (CVHRS), respectively, and a resistance window of ～5349 Ω, ensuring accurate bit-level distinction (Fig. 6). The MRAM device also exhibits robust noise margins (NM ≈ 50.5), confirming its suitability for logic-in-memory operations. On the CIFAR-10 dataset, the accelerator achieves a classification accuracy of 90.66%, with only a 1.18% reduction compared with the floating-point software baseline (Fig. 9, Fig. 10). The final design achieves a peak throughput of 32.31 GOPS and a peak energy efficiency of 494.56 GOPS/W at 133 MHz, exceeding several state-of-the-art designs (Table 2). Conclusions To address the high computational complexity and energy consumption of traditional convolutional multiply–accumulate operations, this study proposes an MRAM-based AdderNet hardware accelerator that incorporates L1-norm computation and sparsity optimization strategies. At the circuit level, an in-situ absolute difference computation method based on STT-MRAM is introduced, together with a magnetic resistance state-mapped full-adder circuit that enables fast and configurable carry and sum computations. Building on these units, a scalable parallel full-adder array is constructed to replace multiplications with lightweight additions, and the complete accelerator is implemented with integrated peripheral circuits. Simulation results validate the proposed design. On the same benchmark dataset, the accelerator achieves an accuracy of 90.66% through circuit–algorithm co-optimization, with accuracy degradation limited to 1.18% compared with the software reference model. Although the training process shows periodic local oscillations, the overall convergence trend follows an exponential decay pattern. The architecture ultimately achieves a peak throughput of 32.31 GOPS and a peak energy efficiency of 494.56 GOPS/W at 133 MHz, exceeding conventional approaches in both performance and energy efficiency.
- Magnetoresistive Random Access Memory (MRAM),
- AdderNet,
- Sparse computation,
- Hardware accelerator,
- Artificial intelligence

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References(16)

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