High-Performance Hardware Design of Arithmetic Coding for Deep Neural Network-Based Image Compression

SONG Sai; CUI Zhao; ZHAN Yinseng; YANG Jinzhen; LU Ming; TIAN Jing

doi:10.11999/JEIT250509

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SONG Sai, CUI Zhao, ZHAN Yinseng, YANG Jinzhen, LU Ming, TIAN Jing. High-Performance Hardware Design of Arithmetic Coding for Deep Neural Network-Based Image Compression[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250509

Citation:

SONG Sai, CUI Zhao, ZHAN Yinseng, YANG Jinzhen, LU Ming, TIAN Jing. High-Performance Hardware Design of Arithmetic Coding for Deep Neural Network-Based Image Compression[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250509

Citation:

SONG Sai, CUI Zhao, ZHAN Yinseng, YANG Jinzhen, LU Ming, TIAN Jing. High-Performance Hardware Design of Arithmetic Coding for Deep Neural Network-Based Image Compression[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250509

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High-Performance Hardware Design of Arithmetic Coding for Deep Neural Network-Based Image Compression

doi: 10.11999/JEIT250509 cstr: 32379.14.JEIT250509

1.
School of Integrated Circuits, Nanjing University, Suzhou 215163, China
2.
School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China

Funds: The National Cryptography Science Foundation(2025NCSF02002), Key Project of Jiangsu Provincial Basic Research Program(BK20243038), China Association for Science and Technology (CAST) Young Elite Scientists Sponsorship Program(2023QNRC001), Jiangsu Youth Fund(BK20241226)

Received Date: 2025-06-04
Rev Recd Date: 2025-09-06

Available Online: 2025-09-19

Abstract

Abstract

Objective Deep Neural Network (DNN)-based image compression has gained increasing importance in real-time applications such as intelligent driving, where an efficient balance between compression ratio and encoding speed is essential. This study proposes a hardware implementation of entropy coding, realized on a Field-Programmable Gate Array (FPGA) platform based on Range Asymmetric Numeral Systems (RANS) arithmetic coding. The design seeks to achieve an optimal trade-off between compression efficiency and hardware resource utilization, while maximizing data throughput to meet the requirements of real-time environments. The main objectives are to enhance image encoding throughput, reduce hardware resource consumption, and sustain high data throughput with only minor losses in compression ratio. The proposed hardware architecture demonstrates strong scalability and practical deployment potential, offering significant value for DNN-based image compression in high-performance systems. Methods To enable practical FPGA deployment of RANS arithmetic coding, several hardware-oriented optimizations are applied. Division and modulus operations in the state update are replaced with precomputed reciprocals combined with fixed-point multiply-and-shift sequences. A precision-calibration stage based on remainder-boundary checks corrects substitution errors to ensure exact quotient–remainder equivalence with full-precision division. This calibration is implemented synchronously in the encoder datapath with minimal control overhead to preserve lossless decoding. Parameter storage and lookup overheads are reduced through fine-grained quantization and a compact, flattened Cumulative Distribution Function (CDF) layout, CDF values are linearly scaled and quantized to fixed-width integers, while contiguous storage of valid entries together with stored effective lengths eliminated padding. Tailored bit-width assignments for different parameter types balance precision against resource usage. These measures reduce the CDF table size from 31.125 KB to 6.369 KB while simplifying lookup logic and shortening critical memory-access paths. Throughput is further increased by using an interleaved multi-channel architecture in which the input stream is partitioned into independent substreams processed concurrently by separate RANS encoder instances. Each instances maintain its own local state, parameter memory, and renormalization buffer. Local handling of renormalization and escape conditions preserves channel continuity, enabling the decoder to perform symmetric decoding without global synchronization. Finally, the entire design is organized as a pipeline-friendly datapath. Reciprocal multiplications are mapped to DSP blocks, while lookups and calibration checks occupy adjacent pipeline stages. Renormalized bytes are emitted to an output FIFO to avoid stalls. This eliminates multi-cycle divide units, reduces latency and memory footprint, and provide a scalable path to high-frequency, high-throughput operation. Results and Discussions The proposed model is deployed on a Xilinx Kintex-7 XC7K325T FPGA platform, synthesized using Vivado v2018.2 and functionally verified on ModelSim SE-64 10.4. Data throughput, resource utilization, and compression efficiency are emphasized in the evaluation. Simulation results indicate that the implemented encoder achieves an identical compression ratio to the PyTorch-based open-source CompressAI library. Any degradation in compression efficiency caused by high parallelism is negligible for high-resolution images (≥768 × 512) (Fig. 5). The FPGA implementation further shows that timing closure is met at a 140 MHz clock frequency. In single-channel mode, the design consumes only 540 LUTs, 336 FFs, and 9.5 BRAMs. Under high-parallelism configurations, resource utilization scales linearly with the number of channels. In eight-channel parallel mode, the encoder attains a symbol throughput of 191.97 M Symbols/s and a data throughput of 4.607 Gbps, representing an improvement of approximately 766% over single-channel operation (Table 3). To quantitatively evaluate the trade-off between resource usage and encoding efficiency, the metric Area Efficiency (AE) is introduced. When compared with FPGA implementations of other entropy coding schemes, the proposed architecture demonstrates clear advantages in both resource efficiency and throughput, achieving an AE of 85.97 K Symbol/(s × Slice), which exceeds most existing high-throughput models. Relative to comparable entropy coding schemes, the proposed design provides a significant increase in throughput (Table 4). Moreover, the scalability and adaptability of the architecture are validated across different degrees of parallelism, enabling flexible adjustment of channel count while maintaining superior performance in diverse application scenarios. Conclusions This work proposes a high-throughput RANS arithmetic coding hardware architecture for DNN-based image compression and demonstrates its implementation on an FPGA platform. By integrating hardware-friendly division substitution, fine-grained parameter quantization, and continuous-output interleaved parallelism, the design overcomes key bottlenecks related to computational latency and resource overhead. Experimental results confirm that the proposed model achieves a peak throughput of 191.97 M symbols/s with negligible compression loss, while also demonstrating outstanding AE and linear scalability. The architecture provides significant advantages over existing entropy coding implementations in both resource-constrained and high-performance scenarios, offering strong practical potential for real-time neural network image compression systems. Overall, this research delivers a pragmatic and extensible solution for the hardware realization of DNN-based image compression, with the capability to accelerate large-scale deployment in high-efficiency environments such as intelligent driving.
- Entropy coding,
- Image compression,
- FPGA,
- Range Asymmetric Numeral System(RANS)

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References(24)

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