Design of Low-Power On-Chip Cache for Visual Perception Systems on the Edge

CHEN Mo; ZHANG Jing; WANG Yanrong; NAZHAMAITI Maimaiti; QIAO Fei

doi:10.11999/JEIT250466

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CHEN Mo, ZHANG Jing, WANG Yanrong, NAZHAMAITI Maimaiti, QIAO Fei. Design of Low-Power On-Chip Cache for Visual Perception Systems on the Edge[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250466

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CHEN Mo, ZHANG Jing, WANG Yanrong, NAZHAMAITI Maimaiti, QIAO Fei. Design of Low-Power On-Chip Cache for Visual Perception Systems on the Edge[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250466

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Design of Low-Power On-Chip Cache for Visual Perception Systems on the Edge

doi: 10.11999/JEIT250466 cstr: 32379.14.JEIT250466

1.
School of Integrated Circuits, North China University of Technology, Beijing 100144, China
2.
Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

Funds: The Beijing Natural Science Foundation (L253009), The Key Research and Development Program of Xinjiang Uygur Autonomous Region (2022B01008-3), The National Natural Science Foundation of China (92164203, 62334006)

Received Date: 2025-05-27
Rev Recd Date: 2025-08-28

Available Online: 2025-09-02

Abstract

Abstract

Objective The proliferation of Internet of Things (IoT) devices and the growing demand for edge computing have driven increased reliance on edge systems. However, deploying compute-intensive tasks on resource-constrained edge devices significantly raises computational demands and power consumption, thereby placing additional strain on energy-limited terminals. On-chip cache, which temporarily stores frequently accessed data and instructions, plays a crucial role in reducing latency and improving system performance. To address the stringent requirements of edge environments, it is essential to design on-chip caches that offer low power consumption, low manufacturing cost, and stable performance. Methods The proposed on-chip cache employs SRAM-based storage cells and a block-based architecture to store intermediate data between neural network layers. The memory capacity is configured as 40.5 Kb, based on the output feature map of the first neural network layer, which generates the largest data volume. This feature map has spatial dimensions of 72×72 with 8 channels. To enable efficient data scheduling during neural network computation, data from each channel is stored in an independent sub-array. Therefore, the buffer consists of 8 sub-arrays, each implemented as a 72×72 SRAM array with dedicated bit-line and word-line drivers. A memory control module is implemented to exploit the progressive reduction in data volume across convolutional layers. During access to the second convolutional layer, only the required sub-arrays are activated. Unused memory blocks are dynamically powered down by the control module to achieve deep power optimization. Performance evaluation is carried out through simulations using TSMC 180 nm CMOS technology. The evaluation includes measurements of access latency under different process corners and temperatures; read/write dynamic power consumption under varying supply voltages, temperatures, and clock frequencies; and a comparative analysis of dynamic power consumption between monolithic and block-based storage architectures. Results and Discussions The proposed on-chip cache demonstrates strong performance across key evaluation metrics. First, a comprehensive design summary is provided, detailing supply voltage, memory capacity, and layout area under different process variations (Table 1). Second, dynamic read/write power measurements under varying operating temperatures, supply voltages, and clock frequencies (Tables 2–4) confirm excellent energy efficiency, satisfying the stringent power-performance requirements of edge visual sensing applications across diverse conditions. Access latency analysis further confirms stable memory read/write behavior under process corner variations and thermal fluctuations (Fig. 8). A comparative evaluation of power consumption between monolithic and partitioned storage architectures (Table 5), together with benchmarking against state-of-the-art designs (Table 6), demonstrates that the proposed cache achieves significantly lower read/write energy consumption at the same process node, while maintaining stable access characteristics at reduced operating voltages. This design adopts a system-level optimization strategy that emphasizes architectural innovation over costly process scaling. When implemented in more advanced technology nodes, the architecture is expected to achieve substantial gains in energy-per-access, minimum operating voltage, and area efficiency. Conclusions This paper presents the architecture and circuit-level design of an on-chip cache tailored for edge visual perception systems. By optimizing the cache structure for neural network workloads, the proposed design reduces dynamic power consumption through block-based storage and dynamic memory control, thereby enhancing energy efficiency and extending operational endurance. The approach offers broad applicability for edge-based visual perception devices.
- On-Chip Cache,
- Low Power Design,
- SRAM

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References(21)

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