Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure

WANG Pengjun; REN Mingze; CHEN Bo; HU Shuang

doi:10.11999/JEIT250360

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WANG Pengjun, REN Mingze, CHEN Bo, HU Shuang. Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250360

Citation:

WANG Pengjun, REN Mingze, CHEN Bo, HU Shuang. Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250360

WANG Pengjun, REN Mingze, CHEN Bo, HU Shuang. Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250360

Citation:

WANG Pengjun, REN Mingze, CHEN Bo, HU Shuang. Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250360

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Low-Cost and High-Security PUF Circuit Based on Cross-Coupling Structure

doi: 10.11999/JEIT250360 cstr: 32379.14.JEIT250360

1.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: The National Natural Science Foundation of China (62174121, 62234008, 62374117), “Vanguard Geese Leading and X” Science and Technology Program of Zhejiang Province (2025C01063)

Received Date: 2025-05-06
Rev Recd Date: 2025-08-28

Available Online: 2025-09-02

Abstract

Abstract

Objective Physical Unclonable Functions (PUFs) serve as unique chip identifiers and have broad application in resource-constrained Internet of Things (IoT) devices. Strong PUFs are widely adopted for device authentication and state verification due to their capacity to generate exponential Challenge–Response Pairs (CRPs). However, the deterministic relationship between input and output arising from their physical construction renders them vulnerable to machine learning attacks. Attackers can model this relationship by collecting a subset of CRPs and applying algorithms such as Logistic Regression (LR), Support Vector Machines (SVM), or Artificial Neural Networks (ANN), enabling prediction of unseen CRPs. The arbiter PUF is the most representative strong PUF. To enhance its security, researchers typically employ XOR architectures or algorithmic obfuscation to increase response complexity. However, these approaches incur substantial hardware overhead, particularly when implemented in circuit form. In this study, we propose a high-security, low-cost PUF based on a cross-coupling structure that enhances resistance to machine learning attacks. The design leverages competition between bistable elements to transition from a reset to a stable state, producing exponential CRPs. Each PUF unit comprises two NOR gates and two access transistors. An XOR tree further obfuscates the output, increasing nonlinearity. Although the XOR tree requires multiple parallel outputs, the design remains compatible with embedded memory architectures such as SRAM, enabling macro-level integration. Overall, this architecture achieves improved attack resistance with minimal additional hardware, as the primary cost lies in a limited number of XOR gates. Methods A strong PUF based on a cross-coupled structure is proposed by analyzing the transient behavior of cross-coupled NOR and NAND gates transitioning from a reset state to a stable state. In this design, the word line serves as the excitation signal, and exponential CRPs are generated by sequentially traversing the word line with a fixed bit width. The implementation focuses on cross-coupled NOR gates as a representative case. Before the PUF response is generated, a reset signal drives the storage nodes of the cross-coupled NOR gates to a low level. Different digital word lines are then activated to provide excitation, while the bit lines are pre-discharged to ground. Upon deactivation of the reset signal, due to inherent process variation—specifically, mismatch in device characteristics—each activated NOR gate exhibits a unique transient response. The mismatch in strengths between different units causes competing voltage transitions at the storage nodes, resulting in a final logic state of 0 or 1 on the corresponding bit line. To reveal the intrinsic entropy mechanisms, the system is modeled by decomposing the entropy sources using the superposition principle. Two independent contributors are identified: (1) variation in charging speed induced by PMOS parasitic capacitance mismatch and (2) difference in positive feedback triggering priority due to NMOS threshold voltage mismatch. The final PUF response arises from the combined effect of these two factors. To enhance resistance to machine learning attacks, multi-bit parallel outputs from the PUF array are processed through an XOR tree. This obfuscation increases response nonlinearity, thereby improving both uniqueness and randomness while rendering the PUF immune to modeling attacks such as those based on LR, SVM, or neural networks. Results and Discussions Simulation results confirm that the proposed cross-coupled strong PUF effectively resists machine learning-based modeling attacks while maintaining favorable statistical properties in reliability, uniqueness, and randomness. The architecture demonstrates strong resilience against modeling attacks from widely used algorithms, including LR, SVM, convolutional neural networks, and ANN (Fig. 7). The average inter-slice Hamming distance is 0.4991 (standard deviation: 0.022), indicating excellent uniqueness (Fig. 8). The average intra-slice Hamming distance is 0.0926 (mean: 0.0116), confirming strong reproducibility. Output logic levels are evenly distributed, with logic 0 and logic 1 accounting for 49.97% and 50.03% of responses, respectively. The minimum Shannon entropy exceeds 0.99, and overall randomness reaches 97.64% (Figs. 9 and 10), indicating near-ideal entropy characteristics. Autocorrelation analysis shows a limit within ±0.02, aligning with the 95% confidence interval of Gaussian white noise and suggesting negligible correlation among response bits (Fig. 11). The native error rate increases from 0.9% before XOR obfuscation to 5.9% after obfuscation, reflecting the trade-off between enhanced security and response stability. Under voltage and temperature variations, the worst-case error rates after XOR obfuscation are 13.55% and 12.21%, respectively (Fig. 12), indicating robust reliability across environmental conditions. A comparative evaluation with existing strong PUF architectures is summarized in Table 1, highlighting the advantages of the proposed design in both security performance and hardware efficiency. Conclusions This study investigates the transition dynamics of bistable circuits from metastable to steady states and integrates delay-based and threshold voltage–based entropy sources to enhance the complexity of strong PUF models. The implementation of XOR tree obfuscation further increases output nonlinearity, reduces hardware overhead, and strengthens resistance to machine learning attacks. Experimental results demonstrate that, even when trained on 10⁴ CRPs, machine learning algorithms such as LR, SVM, and ANN fail to predict PUF responses. The proposed design also exhibits favorable statistical properties and strong reliability. Its structural compatibility with memory architectures makes it particularly suitable for secure authentication in memory-based IoT devices.
- Cross-coupled structures,
- Machine learning,
- High security,
- Strong Physical Unclonable Function (PUF)

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References(15)

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