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XU Mengfan, ZHANG Yuejun, LIU Tianxiang, PAN Yu. Bit-configurable Physical Unclonable Function Circuit Based on Self-detection and Repair Method[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250359
Citation: XU Mengfan, ZHANG Yuejun, LIU Tianxiang, PAN Yu. Bit-configurable Physical Unclonable Function Circuit Based on Self-detection and Repair Method[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250359

Bit-configurable Physical Unclonable Function Circuit Based on Self-detection and Repair Method

doi: 10.11999/JEIT250359 cstr: 32379.14.JEIT250359
Funds:  The National Natural Science Foundation of China (62474100, 62174121, 62134002), “Vanguard Geese Leading and X” Science and Technology Program of Zhejiang Province (2025C01063), The Key R&D Program of Ningbo Science and Technology Yongjiang 2035 (2024Z139), The Key R&D Program of Cixi(CZ2025006)
  • Received Date: 2025-05-06
  • Rev Recd Date: 2025-07-28
  • Available Online: 2025-08-04
  •   Objective  The proliferation of Internet of Things (IoT) devices has intensified the need for robust, hardware-level security. Among hardware-based security primitives, Physical Unclonable Functions (PUFs) serve a critical role in lightweight authentication and dynamic key generation by leveraging inherent process variations to produce unique, unclonable responses. Achieving reliable PUF performance under environmental fluctuations—such as temperature and supply voltage variation—requires balancing sensitivity to process variations with environmental robustness. Conventional approaches, including circuit-level stabilization and architecture-level error correction, can improve reliability but often increase area, power, and test complexity. To overcome these drawbacks, recent work has explored voltage or bias perturbation for unstable response correction. However, entropy degradation during mode transitions in dual-mode PUFs remains a major concern, compromising both reliability and energy efficiency. This study proposes a bit-configurable bistable electric bridge-divider PUF that addresses these challenges by maintaining entropy independence between operational modes, reducing error correlation, and limiting repair and masking overhead. The proposed solution improves randomness, reliability, and energy efficiency, making it suitable for secure, cost-effective authentication in IoT edge devices operating under dynamic conditions.  Methods  Hardware overhead and testing complexity associated with conventional PUF stabilization techniques are reduced by introducing a bit-configurable bistable electric bridge-divider PUF architecture. Entropy generation is enhanced by amplifying process-induced variations through electric bridge imbalance and the exponential behavior of subthreshold current. A reconfigurable bit-cell is employed to enable seamless switching between electric bridge mode and voltage divider mode without additional layout cost; dual-mode operation is thus supported while preserving area efficiency. A voltage-skew-based self-detection and repair mechanism is integrated to dynamically identify and mitigate unstable responses, thereby improving reliability under varying environmental conditions. The PUF circuit is fully custom-designed and fabricated in the TSMC 28 nm CMOS process. Post-layout simulations confirm the robustness of the architecture, demonstrating effective self-repair capabilities and consistent performance under temperature and voltage fluctuations.  Results and Discussions  The proposed design is fabricated using the TSMC 28 nm CMOS process. The total layout area measures 3,283.3 μm2, and each PUF cell occupies 0.7888 μm2 (Fig. 11). Simulation waveforms of the self-detection, repair, and masking operations are presented in (Fig. 12). Inter-chip Hamming distance histograms and fitted curves for both electric bridge mode and voltage divider mode are shown in (Fig. 13). Autocorrelation results of the 40,960-bit output are illustrated in (Fig. 14). The randomness of the responses is evaluated using the NIST test suite provided by the U.S. National Institute of Standards and Technology, with the results summarized in (Table 1). The native Bit Error Rate (BER), measured before repair or masking, is analyzed under various temperature and supply voltage conditions (Fig. 15). By dynamically adjusting the voltage skew, precise control of the error correction rate is achieved, leading to a substantial reduction in BER across different environments (Fig. 16). A performance comparison with previously reported designs is provided in (Table 2). After applying the entropy source repair and masking mechanism, the BER converges to below 1.62 × 10-9, approaching the ideal “zero” BER.  Conclusions  A bit-configurable PUF architecture is proposed to address environmental variability and hardware constraints in IoT edge devices. A reconfigurable bit-cell is employed to support dynamic switching between electric bridge mode and voltage divider mode without incurring additional layout cost. Process-induced variations are amplified through bridge imbalance and the exponential behavior of subthreshold current, which enhances the randomness and uniqueness of the PUF responses. A voltage-skew-based self-detection and repair mechanism is integrated to identify and correct unstable responses, effectively reducing the BER under varying environmental conditions. The proposed design, fabricated using the TSMC 28 nm CMOS process, demonstrates high entropy, robustness, and low overhead in terms of area and power consumption. These characteristics make it suitable for secure and lightweight authentication and key generation in resource-constrained IoT systems.
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