MOS-gated Prebond Through-Silicon Via Testing

DOU Xianrui; LIANG Huaguo; HUANG Zhengfeng; LU Yingchun; CHEN Tian; LIU Jun

doi:10.11999/JEIT250285

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DOU Xianrui, LIANG Huaguo, HUANG Zhengfeng, LU Yingchun, CHEN Tian, LIU Jun. MOS-gated Prebond Through-Silicon Via Testing[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250285

Citation:

DOU Xianrui, LIANG Huaguo, HUANG Zhengfeng, LU Yingchun, CHEN Tian, LIU Jun. MOS-gated Prebond Through-Silicon Via Testing[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250285

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MOS-gated Prebond Through-Silicon Via Testing

doi: 10.11999/JEIT250285 cstr: 32379.14.JEIT250285

1.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China
2.
School of Computer Science and Information Engineering (School of artificial Intelligence), Hefei University of Technology, Hefei 230601, China

Funds: The National Natural Science Foundation of China (62027815, 62174048, 62274052), The Key Project of Teaching Reform Research for Postgraduate Education in Anhui Province (2022jyjxggyj053), The Ministry of Education, Industry-University-Research Co-Operation Collaborative Education Project (220802455302758)

Received Date: 2025-04-17
Rev Recd Date: 2025-07-28

Available Online: 2025-08-04

Abstract

Abstract

Objective As the miniaturization of semiconductor chips approaches physical limitations, integrated chip technologies have become essential to meet the demand for high-performance, low-cost devices in the post-Moore era. Through-Silicon Via (TSV) is a key process in advanced packaging that requires precise testing to ensure reliable interconnections. Quantitative test methods can estimate defect sizes based on test responses; however, variations in Process, Voltage, and Temperature (PVT) hinder accurate defect characterization, making the associated overhead of data capture and analysis difficult to justify. Current techniques often require long test time, with some necessitating two test cycles. While leakage defect detection has reached high accuracy, the detection of resistive open defects—sometimes only tens of milliohms in fault-free states—remains inadequate. This study presents a method that improves detection accuracy for resistive open defects and reduces both test area and time overhead, offering a more efficient and practical TSV testing solution. Methods Previous studies indicate that rising-edge testing provides higher resolution than falling-edge testing and enables simultaneous differentiation of multiple defect types. Based on this principle, a symmetric testing scheme through a single rising-edge test is proposed. To reduce the area overhead associated with shared test structures, MOS gates are employed as selection switches. NMOS transistors, due to their strong 0 and weak 1 characteristics, are placed at the driving end to enable rapid discharge and reset of the reference capacitor voltage. PMOS transistors, exhibiting strong 1 and weak 0 characteristics, are positioned at the receiving end to block interference from low-voltage signals. A two-stage comparator is then employed to amplify the voltage difference between the reference capacitor and the test TSV during the charging phase, producing two intermediate voltage levels. These are subsequently converted into standard high or low logic levels by a Schmitt trigger inverter. Based on the output logic level, both the presence and type of defect can be determined from a single test. Results and Discussions The effectiveness of the proposed method is verified through HSPICE simulations using the Nangate 45 nm open cell library. The detection accuracy for different defect types is modulated by adjusting the Width-to-Length (W/L) ratio of the MOS transistors, as shown in (Table 2). For instance, reducing the W/L ratio of NMOS transistors enhances the detection sensitivity to leakage defects. Specific W/L ratios can therefore be selected to meet targeted testing requirements. (Table 3) presents the results under PVT variations. Although the accuracy shows minor fluctuations, these remain within acceptable limits. A temperature variation of approximately 27 °C results in only a 1 Ω deviation in resistive open defect detection, and a 1 MΩ range in leakage defect accuracy. Even under the worst-case PVT condition, the minimum detection threshold for resistive open defects reaches 94 Ω, which exceeds the capability of existing methods. Conclusions A prebond TSV testing scheme based on MOS gating is proposed to address the high area and time overheads and limited accuracy of conventional approaches. The scheme adopts a symmetric structure between the reference capacitor and the test TSV to mitigate capacitance variation caused by fabrication inconsistencies. A two-stage comparator amplifies the voltage difference between the defective TSV and the reference capacitor during charging, thereby enhancing detection resolution. Simulation results indicate that the method detects resistive open defects equal of above 50 Ω and leakage defects equal of below 9 MΩ. Compared with existing methods, the proposed approach significantly reduces both testing area and time. When multiple TSVs share the testing circuitry, only one NMOS and one PMOS transistor are added, further minimizing the average area overhead.
- Integrated chip,
- Through-Silicon Via (TSV),
- Prebond test,
- Comparator

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References(16)

References

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