A Polymorphic Network Backend Compiler for Domestic Switching Chips

TU Huaqing; WANG Yuanhong; XU Qi; ZHU Jun; ZOU Tao; LONG Keping

doi:10.11999/JEIT250132

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TU Huaqing, WANG Yuanhong, XU Qi, ZHU Jun, ZOU Tao, LONG Keping. A Polymorphic Network Backend Compiler for Domestic Switching Chips[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250132

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TU Huaqing, WANG Yuanhong, XU Qi, ZHU Jun, ZOU Tao, LONG Keping. A Polymorphic Network Backend Compiler for Domestic Switching Chips[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250132

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A Polymorphic Network Backend Compiler for Domestic Switching Chips

doi: 10.11999/JEIT250132 cstr: 32379.14.JEIT250132

TU Huaqing^{1, 2},
WANG Yuanhong^{1, 2},
XU Qi^{1, 2},
ZHU Jun^{1, 2},
ZOU Tao^{1, 2
,
,},
LONG Keping^{1, 2}

1.
Zhejiang Laboratory, Hangzhou 310000, China
2.
Institute of Computing Technology Chinese Academy of Sciences, Beijing 100000, China

Funds: National Key Research and Development Project of China (No. 2022YFB2901503), National Natural Science Foundation of China (No. U22A2005), Key R&D Program of Zhejiang (2024SSYS0001), China Postdoctoral Science Foundation (No. 2024M75986).

Received Date: 2025-03-05
Accepted Date: 2025-11-03
Rev Recd Date: 2025-11-03

Available Online: 2025-11-08

Abstract

Abstract

Objective The P4 language and programmable switching chips provide a feasible solution for the deployment of polymorphic networks. However, polymorphic network packets written in P4 cannot be directly executed on the domestically produced TsingMa.MX programmable switching chip from Centec, necessitating the design of a specialized compiler to translate and deploy P4 language onto this chip. Existing backend compilers are primarily designed and optimized for software-programmable switches such as BMv2, FPGAs, and Intel Tofino series chips, making them unsuitable for compiling polymorphic network programs on the TsingMa.MX chip. To address this issue, this paper proposes p4c-TsingMa, a backend compiler tailored for the TsingMa.MX switching chip. This compiler enables the translation of high-level network programming languages into executable formats for the TsingMa.MX chip, allowing it to simultaneously support the parsing and forwarding of multiple types of network modal packets. Methods p4c-TsingMa first employs a preorder traversal method to extract key information such as protocol types, protocol fields, and actions from the Intermediate Representation (IR). Then performs instruction translation, ultimately generating control commands for the TsingMa.MX chip. Additionally, p4c-TsingMa adopts a UDF entry merging method to consolidate matching instructions from different network modalities into a single lookup table, enabling the extraction of multiple modal matching entries in one operation and significantly improving the utilization of chip resources. Results and Discussions This paper implements the p4c-TsingMa compiler using C++, which maps network modal programs written in P4 language into chip configurations for the TsingMa.MX switching chip. A polymorphic network packet testing environment (Fig. 7) is established, where multiple types of network data packets are simultaneously sent to the same port of the switch. The chip, following the flow table configuration, successfully identifies polymorphic network data packets and forwards them to their corresponding ports (Fig. 9). Additionally, the table entry merging algorithm improves register resource utilization by 37.5% to 75%, enabling the chip to process more than two types of modal data packets in parallel. Conclusions This paper designs a polymorphic network backend compiler, p4c-TsingMa, specifically for domestic switching chip. By leveraging the FlexParser and FlexEdit capabilities of the TsingMa chip, the compiler translates polymorphic network programs into TsingMa.MX chip commands, enabling the chip to parse and edit polymorphic data packets. Experimental results demonstrate that p4c-TsingMa achieves high compilation efficiency and improves register resource utilization by 37.5% to 75%.
- Polymorphic Network,
- Programmable Data Plane,
- Domestic Switching Chips,
- Backend Compiler

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References(22)

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