A Test Vector CODEC Scheme Based on BRAM-Segmented Synchronous Table Lookup

YI Maoxiang; ZHANG Jiatong; LU Yingchun; LIANG Huaguo; MA Lixiang

doi:10.11999/JEIT250053

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YI Maoxiang, ZHANG Jiatong, LU Yingchun, LIANG Huaguo, MA Lixiang. A Test Vector CODEC Scheme Based on BRAM-Segmented Synchronous Table Lookup[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250053

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YI Maoxiang, ZHANG Jiatong, LU Yingchun, LIANG Huaguo, MA Lixiang. A Test Vector CODEC Scheme Based on BRAM-Segmented Synchronous Table Lookup[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250053

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A Test Vector CODEC Scheme Based on BRAM-Segmented Synchronous Table Lookup

doi: 10.11999/JEIT250053 cstr: 32379.14.JEIT250053

1.
School of Electrical and Electronic Engineering, Anhui Institute of Information Technology, Wuhu 241199, China
2.
School of Microelectronics, Hefei University of Technology, Hefei 230009, China
3.
State Key Laboratory of Millimeter Waves, Nanjing 210096, China

Funds: The Natural Science Foundation of China (62027815), Open Project of State Key Laboratory of Millimeter Waves (K202530)

Received Date: 2025-01-22
Rev Recd Date: 2025-08-20

Available Online: 2025-08-27

Abstract

Abstract

Objective Logic testing using Automatic Test Equipment (ATE) is a critical step in integrated circuit (IC) manufacturing test to ensure chip quality. Enhancing logic test efficiency is essential to reducing digital IC testing costs. During testing, IC test data are typically stored in the main memory of the ATE user board and sequentially read to generate channel test waveforms. The time required to read test data directly affects test efficiency. Traditional Test Data Compression (TDC) approaches, which often require preprocessing such as X-bit filling, are suited only for scan testing and thus do not meet broader test engineering needs. Meanwhile, advances in Field-Programmable Gate Array (FPGA) technology have enabled the customization of high-speed Block RAM (BRAM) resources. This study proposes a test vector coding scheme based on component statistics, in which the Device Under Test (DUT) test vectors are encoded and corresponding component coding tables are generated and stored in the FPGA BRAM. A table lookup circuit is implemented to achieve synchronous, parallel output of all test vector components, effectively reducing the external data read time and improving logic test efficiency. Methods Each bit symbol in an IC test vector comprises four components: drive (DC), measurement (MC), high impedance (ZC), and residual value (RV). The proposed scheme performs statistical encoding of each component across all bit symbols in the DUT’s test vectors and generates shared DC, MC, and ZC coding tables. The encoding process includes: (1) scanning and extracting each vector from the DUT test project files; (2) determining the bit component values and residual values for all channels; (3) for each component, compiling and deduplicating all generated codes, reassigning deleted code references to reserved codes to form the final coding tables; and (4) determining the combined component addresses and residual values. Using a Xilinx Kintex-7 FPGA development board and the Vivado tool, three BRAM modules are configured, and a BRAM table lookup control circuit is designed (Fig. 4). Prior to testing, the component coding tables are downloaded to the FPGA BRAM, and the combined address and residual values of the three component codes for each test vector are stored in off-chip SDRAM. During operation, the lookup circuit uses the combined address to synchronously and in parallel output the three components, which—together with the residual value—drive the waveform generator to produce the channel test waveform. Results and Discussions The functionality of the BRAM-segmented synchronous table lookup circuit is verified through simulation. Three BRAM modules with 64-bit width and customized segment address depth are configured. The COE files of the component encoding tables are downloaded to the target BRAMs via a UART interface, using address generation control logic. The corresponding addresses are then applied to the lookup circuit. A complete simulation is conducted by integrating the segmented lookup module, data strobe module, address allocation module, and data transmission module, enabling validation of the BRAM data download, segmented table lookup, and I/O processes within the FPGA (Fig. 6–Fig. 8). Results confirm that the synchronized parallel output from the lookup circuit matches the three component codes of the predefined test vectors (Fig. 9–Fig. 13). The SDRAM read time is also analyzed. Under the same configuration parameters, the proposed encoding scheme reduces the read time of each test vector by 66.7% compared with a direct encoding storage scheme (Table 3), indicating a significant improvement in logic test efficiency. A qualitative comparison with traditional TDC schemes—including dictionary coding, Frequency-Directed Run-length (FDR) coding and run-length coding—is presented in Table 4. The results indicate that the proposed scheme, which utilizes high-speed BRAM embedded in modern FPGAs, supports non-scan parallel logic testing with high decoding speed and low overhead, while fully satisfying the original test project requirements. Conclusions A test vector encoding and decoding scheme based on component statistics and BRAM-segmented synchronous table lookup is proposed and implemented. The segmented lookup circuit is designed, and its functional correctness is verified through simulation. Compared with direct encoding, the proposed scheme achieves a 66.7% reduction in logic test time. In contrast to traditional TDC approaches, it offers lower hardware overhead by leveraging embedded high-speed BRAM. The scheme supports ATE-based parallel non-scan logic testing and meets the original engineering design goals, providing a practical foundation for optimizing the logic test function module of the ATE user board.
- Logic test,
- Test vector,
- Component statistical coding,
- BRAM,
- Segmented synchronous table lookup

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References(21)

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