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LIN Yuewei, ZHANG Qixun, WEI Zhiqing, LI Xingwang, LIU Fan, FAN Shaoshuai, WANG Yi. Status and Prospect of Hardware Design on Integrated Sensing and Communication[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240012
Citation: LIN Yuewei, ZHANG Qixun, WEI Zhiqing, LI Xingwang, LIU Fan, FAN Shaoshuai, WANG Yi. Status and Prospect of Hardware Design on Integrated Sensing and Communication[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240012

Status and Prospect of Hardware Design on Integrated Sensing and Communication

doi: 10.11999/JEIT240012
Funds:  The National Natural Science Foundation of China Excellent Youth Science Fund Project (62022020), The National Key R&D Program (2020YFA0711302), The Open Foundation of State Key Laboratory of Networking and Switching Technology (Beijing University of Posts and Telecommunications) (SKLNST-2023-1-14), The Open Foundation of Key Laboratory of Universal Wireless Communications (BUPT), Ministry of Education, P.R.China, The Public Domestic Visiting Program of Qingdao University of Science and Technology
  • Received Date: 2024-01-16
  • Rev Recd Date: 2024-05-03
  • Available Online: 2024-05-12
  • The Integrated Sensing And Communication (ISAC) requires that communication and sensing share the same radio frequency band and hardware resource. The characteristics of multi bands, large bandwidth, communication and sensing’s different requirements for hardware put forward higher requirements for ISAC hardware design. The hardware designs, verification technologies and systemic hardware verification platforms of beyond 5G, 6G and WiFi ISACs are summarized. The relevant hardware designs and verification researches at home and abroad in recent years are summarized also. The hardware design challenges such as the hardware requirement contradictions between communication and sensing systems, the In Band Full Duplex (IBFD) Self-Interference Cancellation (SIC), the Power Amplifier (PA) efficiency, and the more accurate modeling required by circuit performance are paid attention to. First of all, the design of ISAC transceiver architectures in existing researches are summarized and compared. Then, the existing ISAC IBFD self-interference suppression schemes, the low Peak to Average Power Ratio (PAPR) waveform or high-performance PA designs, the high precision device modeling methods and the systemic hardware verification platforms are introduced and analyzed. At last, the full text is summarized, the future open issues for ISAC hardware design are analyzed.
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