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HUANG Jiye, XIAO Qiang, TIAN Dahai, GAO Mingyu, WANG Junfan, DONG Zhekang, HUANG Xiwei. A Reconfigurable 2-D Convolver Based on Triangular Numbers Decomposition[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT231123
Citation: HUANG Jiye, XIAO Qiang, TIAN Dahai, GAO Mingyu, WANG Junfan, DONG Zhekang, HUANG Xiwei. A Reconfigurable 2-D Convolver Based on Triangular Numbers Decomposition[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT231123

A Reconfigurable 2-D Convolver Based on Triangular Numbers Decomposition

doi: 10.11999/JEIT231123
Funds:  National Key Research and Development Program (2022YFD2000100)
  • Received Date: 2023-10-17
  • Rev Recd Date: 2024-02-03
  • Available Online: 2024-02-20
  • Two-Dimensional (2-D) convolution with different kernel sizes enriches the overall performance in computer vision tasks. Currently, there is a lack of an efficient design method of reconfigurable 2-D convolver, which limits the deployment of Convolution Neural Network (CNN) models at the edge. In this paper, a new approach based on multiplication management and triangular numbers decomposition is proposed. The proposed 2-D convolver includes a certain number of Processing Elements (PE) and corresponding control units, where the former is responsible for computing tasks and the latter manages the combination of multiplication operations to achieve different convolution sizes. Specifically, an odd number list is determined based on the application scenario, which represents the supported sizes of the 2-D convolutional kernel. The corresponding triangular number list is obtained using the triangular numbers decomposition method. Then, the total number of PEs is determined based on the triangular number list and computational requirements. Finally, the corresponding control units and the interconnection of PEs are determined by the addition combinations of triangular numbers. The proposed reconfigurable 2-D convolver is designed by Verilog Hardware Description Language (HDL) and implemented by Vivado 2022.2 software on the XCZU7EG board. Compared with similar methods, the proposed 2-D convolver significantly improves the efficiency of multiplication resources, increasing from 20%~50% to 89%, and achieves a throughput of 1 500 MB/s with 514 logic units, thereby demonstrating its wide applicability.
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