Global Ramp Uniformity Correction Method for Super-large Array CMOS Image Sensors

XU Ruiming; GUO Zhongjie; LIU Suiyan; YU Ningmei

doi:10.11999/JEIT231082

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XU Ruiming, GUO Zhongjie, LIU Suiyan, YU Ningmei. Global Ramp Uniformity Correction Method for Super-large Array CMOS Image Sensors[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT231082

Citation:

XU Ruiming, GUO Zhongjie, LIU Suiyan, YU Ningmei. Global Ramp Uniformity Correction Method for Super-large Array CMOS Image Sensors[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT231082

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Global Ramp Uniformity Correction Method for Super-large Array CMOS Image Sensors

doi: 10.11999/JEIT231082

Department of Electronics, Xi'an University of Technology, Xi'an 710048, China

Funds: The National Natural Science Foundation of China (62171367), The Key research and development plan of Shaanxi province (2021GY-060), Shaanxi Innovation Capability Support Project (2022TD-39)

Received Date: 2023-10-08
Rev Recd Date: 2024-02-02

Available Online: 2024-02-29

Abstract

Abstract

Considering the problem of the non-uniformity of the ramp signal in the large-array CMOS Image Sensors (CIS), a ramp uniformity correction method for CMOS image sensors is proposed in this paper. The correction method is based on error storage and level shift ideas. Storage capacitor that are used to store ramp non-uniformity error are introduced in column readout circuit. According to the stored ramp non-uniformity error, the ramp signal of each column is shifted. So as to ensure the uniformity of the ramp signal. Based on the 55 nm 1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixel area arrays is 8192(H)×8192(V), and a single pixel size is 10 μm, the proposed correction method reduces the ramp non-uniformity error from 7.89mV to 36.8 μV. The Differential NonLinearity (DNL) of the ramp signal is +0.001 3/–0.004 LSB and the Integral NonLinearity (INL) is +0.045/–0.02 LSB. The Column Fixed Pattern Noise(CFPN) is reduced from 1.9% to 0.01%. The proposed ramp uniformity correction method reduces the ramp non-uniformity error by 99.54% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. It provides a certain theoretical support for the design of high-precision CMOS image sensors.
- CMOS Image Sensors(CIS),
- Column Fixed Pattern Noise(CFPN),
- Ramp signal generating circuit,
- Ramp uniformity correction method

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References(21)

References

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