In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices

HUI Yajuan; LI Qingzhen; WANG Leimin; LIU Cheng

doi:10.11999/JEIT230815

Volume 46 Issue 6

Jun. 2024

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Article Navigation > Journal of Electronics & Information Technology > 2024 > 46(6): 2673-2680

HUI Yajuan, LI Qingzhen, WANG Leimin, LIU Cheng. In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices[J]. Journal of Electronics & Information Technology, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815

Citation:

HUI Yajuan, LI Qingzhen, WANG Leimin, LIU Cheng. In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices[J]. Journal of Electronics & Information Technology, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815

Citation:

HUI Yajuan, LI Qingzhen, WANG Leimin, LIU Cheng. In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices[J]. Journal of Electronics & Information Technology, 2024, 46(6): 2673-2680. doi: 10.11999/JEIT230815

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In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices

doi: 10.11999/JEIT230815

HUI Yajuan^{1, 2, 3
,
,},
LI Qingzhen^{1, 2, 3},
WANG Leimin^{1, 2, 3},
LIU Cheng⁴

1.
Institute of Automation, China University of Geoscience(Wuhan), Wuhan 430074, China
2.
Key Laboratory of Advanced Control and Intelligent Automation for Complex Systems, Wuhan 430074, China
3.
Engineering Research Center of Intelligent Technology for Geo-Exploration, Ministry of Education, Wuhan 430074, China
4.
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China

Funds: The National Natural Science Foundation of China (62104217)

Received Date: 2023-08-01
Rev Recd Date: 2023-11-26

Available Online: 2023-11-29

Publish Date: 2024-06-30

Abstract

Abstract

In the research on utilizing emerging non-volatile storage arrays for in-memory computing, the latency of in-memory multipliers often exhibits exponential growth with increasing bit width, and significantly impacts the computational performance. A Voltage-Gated Spin-Orbit Torque Magnetoresistive Random-Acess Memory (VGSOT-MRAM) device unit crossbar array is proposed and a circuit design approach for in-memory Wallace tree multipliers is presented in this paper. The proposed series-connected storage unit structure effectively addresses the issue of low resistance values in magnetic storage units through resistive summing. Furthermore, an in-memory computing architecture based on a voltage-controlled spin-orbit torque magnetic storage unit crossbar array is introduced. Finally, a five-input majority decision logic gate implemented during the “read” operation is leveraged to further reduce the logic depth of the Wallace tree multiplier. Compared to existing multiplier design methods, the proposed approach reduces the delay overhead from O(n²) to O(log₂ n), with even lower latency for larger bit widths.

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References(27)

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