A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm

WEN Yi; CHEN Jianjun; HUANG Jun; YAO Xiaohu; LIU Hengzhu

doi:10.11999/JEIT230668

Volume 45 Issue 11

Nov. 2023

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Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(11): 3984-3990

WEN Yi, CHEN Jianjun, HUANG Jun, YAO Xiaohu, LIU Hengzhu. A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm[J]. Journal of Electronics & Information Technology, 2023, 45(11): 3984-3990. doi: 10.11999/JEIT230668

Citation:

WEN Yi, CHEN Jianjun, HUANG Jun, YAO Xiaohu, LIU Hengzhu. A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm[J]. Journal of Electronics & Information Technology, 2023, 45(11): 3984-3990. doi: 10.11999/JEIT230668

Citation:

WEN Yi, CHEN Jianjun, HUANG Jun, YAO Xiaohu, LIU Hengzhu. A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm[J]. Journal of Electronics & Information Technology, 2023, 45(11): 3984-3990. doi: 10.11999/JEIT230668

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A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm

doi: 10.11999/JEIT230668 cstr: 32379.14.JEIT230668

Key Laboratory of Advanced Microprocessor Chips and Systems, College of Computer Science, National University of Defense Technology, Changsha 410073, China

Funds: The National Natural Science Foundation of China (61974163, 62174180)

Received Date: 2023-07-04
Rev Recd Date: 2023-09-24

Available Online: 2023-09-27

Publish Date: 2023-11-28

Abstract

Abstract

A 16 Gbit/s Serializer/Deserializer interface(SerDes) chip which is composed of 4 lanes and 2 Phase-Locked Loop(PLLs), is designed in bulk CMOS technology. A negative impedance structure Continuous Time Linear Equalizer(CTLE) is used in the Analog Front End(AFE) of the receiver to obtain 22.9 dB high frequency gain. Further, 5-tap Decision Feedback Equalizer(DFE) is used to compensate the Inter Symbol Interference(ISI), and tap1 unrolled to obtain sufficient timing constraints. Least Mean Square(LMS) algorithm is used to control adaptive CTLE and DFE compensation coefficient to counter the influence of process, power supply and temperature fluctuations. The measurement results show that, the total power consumption is 615mW when working at 16 Gbit/s. Transmitter output signal eye height is 143 mV, width is 43.8 ps(0.7UI), jitter tolerance of the receiver contents the PCIe4.0 protocol requirements at all frequency, working temperature cover –55°C～125°C, power supply voltage cover 0.9 V±10%, bit error rate is less than 1E-12.

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References(17)

References

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