Hardware Optimization of S-box of Camellia Algorithm Based on Polynomial Basis

LI Yanjun; ZHANG Weiguo; GE Yaodong; WANG Ke

doi:10.11999/JEIT220499

Volume 45 Issue 3

Mar. 2023

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2023 > 45(3): 921-928

LI Yanjun, ZHANG Weiguo, GE Yaodong, WANG Ke. Hardware Optimization of S-box of Camellia Algorithm Based on Polynomial Basis[J]. Journal of Electronics & Information Technology, 2023, 45(3): 921-928. doi: 10.11999/JEIT220499

Citation:

LI Yanjun, ZHANG Weiguo, GE Yaodong, WANG Ke. Hardware Optimization of S-box of Camellia Algorithm Based on Polynomial Basis[J]. Journal of Electronics & Information Technology, 2023, 45(3): 921-928. doi: 10.11999/JEIT220499

Citation:

PDF( 1608 KB)

Hardware Optimization of S-box of Camellia Algorithm Based on Polynomial Basis

doi: 10.11999/JEIT220499

LI Yanjun^{1, 2},
ZHANG Weiguo^{2
,
,},
GE Yaodong²,
WANG Ke²

1.
Information Industry Information Security Evaluation Center, the 15th Research Institute of China Electronics Technology Group Corporation, Beijing 100083, China
2.
Beijing Institute of Electronic Science and Technology, Beijing 100070, China

Funds: The Open Project of Guangxi Key Labtorary of Cryptography and Information Security (GCIS201912), The Advanced Discipline Construction Project of Beijing Universities (20210101Z0401)

Received Date: 2022-04-22
Rev Recd Date: 2022-05-23

Available Online: 2022-05-30

Publish Date: 2023-03-10

Abstract

Abstract

An algebraic expression for the S-box of Camellia’s algorithm based on irreducible polynomials is proposed in this paper, and eight different isomorphic expressions are also given. Then combined with the characteristics of S-box, an optimization scheme based on polynomial basis is given by theoretical proof, in which some redundant linear operations are reduced. Compared with the same gate-limited scheme the circuit area is saved by 9.12% in the Semiconductor Manufacturing International Corporation (SMIC) 130 nm process library and by 8.31% in the SMIC 65 nm process library. Finally, according to the computational redundancy in the design of the S-box of Camellia algorithm, two completely equivalent representations on the finite field are given, which will have a positive impact on the optimization of the S-box of Camellia algorithm.
- Finite field,
- Polynomial basis,
- Normal basis,
- Camellia algorithm,
- S-box

FullText(HTML)

References(20)

References

[1]	BOGDANOV A, KNUDSEN L R, LEANDER G, et al. PRESENT: An ultra-lightweight block cipher[C]. Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10–13, 2007, Proceedings, Berlin, Heidelberg, Germany, 2007.
[2]	WU Wenling and ZHANG Lei. LBlock: A lightweight block cipher[C]. The 9th International Conference on Applied Cryptography and Network Security, Berlin, Heidelberg, Germany, 2011.
[3]	CHEN Shiyao, FAN Yanhong, SUN Ling, et al. SAND: An AND-RX Feistel lightweight block cipher supporting S-box-based security evaluations[J]. Designs, Codes and Cryptography, 2021, 90(1): 155–198. doi: 10.1007/s10623-021-00970-9
[4]	FENG Jingya and LI Lang. SCENERY: A lightweight block cipher based on Feistel structure[J]. Frontiers of Computer Science, 2022, 16(3): 163813. doi: 10.1007/S11704-020-0115-9
[5]	GUO Ying, LI Lang, and LIU Botao. Shadow: A lightweight block cipher for IoT nodes[J]. IEEE Internet of Things Journal, 2021, 8(16): 13014–13023. doi: 10.1109/JIOT.2021.3064203
[6]	AOKI K, ICHIKAWA T, KANDA M, et al. Camellia: A 128-bit block cipher suitable for multiple platforms-design and analysis[C]. 7th International Workshop on Selected Areas in Cryptography, Berlin Heidelberg, Germany, 2000.
[7]	SATOH A and MORIOKA S. Hardware-focused performance comparison for the standard block ciphers AES, camellia, and triple-DES[C]. 6th International Conference on Information Security, Berlin, Heidelberg, Germany, 2003: 252–266.
[8]	ZOU Jian, WEI Zihao, SUN Siwei, et al. Some efficient quantum circuit implementations of Camellia[J]. Quantum Information Processing, 2022, 21(4): 131. doi: 10.1007/S11128-022-03477-X
[9]	WEI Z, SUN S, HU L, et al. Scrutinizing the tower field implementation of the GF(2^8) inverter--with applications to AES, Camellia, and SM4[J]. Cryptology ePrint Archive, 2019.
[10]	CI C W, NAZIRI S Z M, ISMAIL R C, et al. Crypto-core design using camellia cipher[J]. Journal of Physics:Conference Series, 2021, 1755(1): 012019. doi: 10.1088/1742-6596/1755/1/012019
[11]	RASHIDI B. Compact and efficient structure of 8-bit S-box for lightweight cryptography[J]. Integration, 2021, 76: 172–182. doi: 10.1016/j.vlsi.2020.10.009
[12]	DAEMEN J and RIJMEN V. The Rijndael block cipher: AES proposal[C]. First Candidate Conference (AeS1), 1999: 343–348.
[13]	LIU Fen, JI Wen, HU Lei, et al. Analysis of the SMS4 block cipher[C]. Information Security and Privacy, 12th Australasian Conference, ACISP 2007, Townsville, Australia, July 2–4, 2007, Proceedings, Berlin, Heidelberg, Germany, 2007.
[14]	SATOH A, MORIOKA S, TAKANO K, et al. A compact Rijndael hardware architecture with S-box optimization[C]. 7th International Conference on the Theory and Application of Cryptology and Information Security, Berlin, Heidelberg, Germany, 2001: 239–254.
[15]	MAXIMOV A and EKDAHL P. New circuit minimization techniques for smaller and faster AES SBoxes[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019: 91–125. doi: 10.46586/tches.v2019.i4.91-125
[16]	MARTÍNEZ-HERRERA A F, MEX-PERERA J C, and NOLAZCO-FLORES J A. Some representations of the S-Box of Camellia in GF (((2²)²)²)[C]. 11th International Conference on Cryptology and Network Security, Berlin, Heidelberg, Germany, 2012: 296–309.
[17]	SATOH A and MORIOKA S. Unified hardware architecture for 128-bit block ciphers AES and Camellia[C]. 5th International Workshop on Cryptographic Hardware and Embedded Systems, Berlin, Heidelberg, Germany, 2003: 304–318.
[18]	魏子豪, 张英杰, 胡磊, 等. Camellia算法S盒的紧凑硬件实现[J]. 密码学报, 2021, 8(5): 844–855. doi: 10.13868/j.cnki.jcr.000481 WEI Zihao, ZHANG Yingjie, HU Lei, et al. A compact hardware implementation of S-Box for Camellia[J]. Journal of Cryptologic Research, 2021, 8(5): 844–855. doi: 10.13868/j.cnki.jcr.000481
[19]	BOYAR J, FIND M G, and PERALTA R. Small low-depth circuits for cryptographic applications[J]. Cryptography and Communications, 2019, 11(1): 109–127. doi: 10.1007/s12095-018-0296-3
[20]	刘建. 两类密码组件的实现优化方法研究[D]. [硕士论文], 战略支援部队信息工程大学, 2019. LIU Jian. Optimization on the implementation of two types of cryptographic components [D]. [Master dissertation], PLA Strategic Support Force Information Engineering University, 2019.