Design of Hardware IP Core Security Protection Based on Multi-Level Co-obfuscation

Huihong ZHANG; Jing LI; Qiufeng WU; Yuejun ZHANG; Pengjun WANG

doi:10.11999/JEIT210631

Volume 43 Issue 9

Sep. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(9): 2458-2465

Huihong ZHANG, Jing LI, Qiufeng WU, Yuejun ZHANG, Pengjun WANG. Design of Hardware IP Core Security Protection Based on Multi-Level Co-obfuscation[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2458-2465. doi: 10.11999/JEIT210631

Citation:

Huihong ZHANG, Jing LI, Qiufeng WU, Yuejun ZHANG, Pengjun WANG. Design of Hardware IP Core Security Protection Based on Multi-Level Co-obfuscation[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2458-2465. doi: 10.11999/JEIT210631

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Design of Hardware IP Core Security Protection Based on Multi-Level Co-obfuscation

doi: 10.11999/JEIT210631

1.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China

Funds: The National Natural Science Foundation of China (61874078, 61871244), The Fundamental Research Funds for the Provincial Universities of Zhejiang (SJLY2020015), The S&T Plan of Ningbo Science and Technology Department (202002N3134), Ningbo Natural Science Foundation (202003N4107)

Received Date: 2021-06-28
Rev Recd Date: 2021-08-20

Available Online: 2021-08-24

Publish Date: 2021-09-16

Abstract

Abstract

Most of the reported hardware obfuscations are single-level ones focusing on physical level, logical level or behavior level, in which the lack of synergy among different levels commonly results in limited security performance. Based on study of the relationships among circuit layout, logic and states transition, a multi-level co-obfuscation scheme is proposed to protect hardware IP cores. In bottom-up collaborative confusion design, dummy vias are introduced into camouflage gates layout to perform physical-logic obfuscation, and via-PUF (Physical Unclonable Fuction) are utilized in state transition control to realize physical-behavior obfuscation. Then, in top-down collaborative obfuscation design, logic locks are used to perform behavior-logic obfuscation, and parallel-branch obfuscation wire technique is designed to complete the behavior-physical confusion. Finally, a substitution algorithm of the obfuscation gates into the circuit’s netlist is proposed, and the three-level cooperative obfuscation is realized to achieve IP core security protection. ISCAS-89 Benchmarks and a typical cryptogram algorithm are used to verify the correctness and efficiency of the proposed IP core protection scheme. The test results show that under TSMC 65nm process, the average area cost percentage of the proposed co-obfuscation in large-scale circuits is 11.7%, the average power consumption accounts for 5.1%, The difference of register toggle between correct and wrong keys is less than 10%, and the proposed scheme can effectively resist violence attack, reverse engineering, boolean SATisfiability (SAT) attack.
- Hardware security,
- IP core protection,
- Hardware obfuscation,
- Multi-level co-obfuscation

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References(14)

References

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