Advanced Search
Volume 43 Issue 9
Sep.  2021
Turn off MathJax
Article Contents
Xiaotong CUI, Weirong QIN, Kefei CHENG, Yu WU. The Vulnerability Analysis of Design-for-trust Technique and Its Defense[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2482-2488. doi: 10.11999/JEIT210624
Citation: Xiaotong CUI, Weirong QIN, Kefei CHENG, Yu WU. The Vulnerability Analysis of Design-for-trust Technique and Its Defense[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2482-2488. doi: 10.11999/JEIT210624

The Vulnerability Analysis of Design-for-trust Technique and Its Defense

doi: 10.11999/JEIT210624
Funds:  The Science and Technology Research Program of Chongqing Municipal Education Commission (KJQN201900641), The State Key Laboratory of Computer Architecture Research Fund (CARCH201902), The State Key Laboratory of Vehicle NVH and Safety Technology Research Fund (NVHSKL-202114)
  • Received Date: 2021-06-28
  • Rev Recd Date: 2021-08-12
  • Available Online: 2021-08-27
  • Publish Date: 2021-09-16
  • System-on-Chip (SoC) designers typically use third Party Intellectual Property(3PIP) cores to implement target functions. As these 3PIP cores are not trusted, the underlying SoC suffers from the threat of Hardware Trojans(HTs). As a subset of design-for-trust techniques, the diversified redundancy is promising in establishing trustworthy computings of SoCs. However, It is shown that the diversified redundancy can be defeated by HTs that explores triggering patterns. Therefore, an adapted diversified redundancy technique is proposed to defend against such kind of attacks.
  • loading
  • [1]
    BHUNIA S and TEHRANIPOOR M. Hardware Security: A Hands-on Learning Approach[M]. Cambridge: Morgan Kaufmann Publishers, 2018.
    [2]
    XIAO K, FORTE D, JIN Y, et al. Hardware Trojans: Lessons learned after one decade of research[J]. ACM Transactions on Design Automation of Electronic Systems, 2016, 22(1): 6.
    [3]
    ZHANG Jiliang and QU Gang. Recent attacks and defenses on FPGA-based systems[J]. ACM Transactions on Reconfigurable Technology and Systems, 2019, 12(3): 14.
    [4]
    LU Renjie, SHEN Haihua, FENG Zhihua, et al. HTDet: A clustering method using information entropy for hardware Trojan detection[J]. Tsinghua Science and Technology, 2021, 26(1): 48–61. doi: 10.26599/TST.2019.9010047
    [5]
    HU Nianhang, YE Mengmei, and WEI Sheng. Surviving information leakage hardware Trojan attacks using hardware isolation[J]. IEEE Transactions on Emerging Topics in Computing, 2019, 7(2): 253–261. doi: 10.1109/TETC.2017.2648739
    [6]
    ZHANG Xuehui and TEHRANIPOOR M. Case study: Detecting hardware Trojans in third-party digital IP cores[C]. 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, USA, 2011: 67–70.
    [7]
    AMIN H A M, ALKABANI Y, and SELIM G M I. System-level protection and hardware Trojan detection using weighted voting[J]. Journal of Advanced Research, 2014, 5(4): 499–505. doi: 10.1016/j.jare.2013.11.008
    [8]
    RAJENDRAN J, ZHANG Huan, SINANOGLU O, et al. High-level synthesis for security and trust[C]. The 19th International on-Line Testing Symposium, Chania, Greece, 2013: 232–233.
    [9]
    RAJENDRAN J J V, SINANOGLU O, and KARRI R. Building trustworthy systems using untrusted components: A high-level synthesis approach[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(9): 2946–2959. doi: 10.1109/TVLSI.2016.2530092
    [10]
    CUI Xiaotong, MA Kun, SHI Liang, et al. High-level synthesis for run-time hardware Trojan detection and recovery[C]. The 51st ACM/EDAC/IEEE Design Automation Conference, San Francisco, USA, 2014: 1–6.
    [11]
    CUI Xiaotong, ZHANG Xing, YAN Hao, et al. Towards building and optimizing trustworthy systems using untrusted components: A graph-theoretic perspective[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, To be published. doi: 10.1109/TCAD.2021.3086765.
    [12]
    GUNDABOLU S and WANG Xiaofang. On-chip data security against untrustworthy software and hardware IPs in embedded systems[C]. 2018 IEEE Computer Society Annual Symposium on VLSI, Hong Kong, China, 2018: 644–649.
    [13]
    SAYED-AHMED A, HAJ-YAHYA J, and CHATTOPADHYAY A. SoCINT: Resilient system-on-chip via dynamic intrusion detection[C]. The 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, Delhi, India, 2019: 359–364.
    [14]
    CUI Xiaotong, SAEED S M, ZULEHNER A, et al. On the difficulty of inserting Trojans in reversible computing architectures[J]. IEEE Transactions on Emerging Topics in Computing, 2020, 8(4): 960–972.
    [15]
    KARNIK T and HAZUCHA P. Characterization of soft errors caused by single event upsets in CMOS processes[J]. IEEE Transactions on Dependable and secure Computing, 2004, 1(2): 128–143. doi: 10.1109/TDSC.2004.14
    [16]
    GAILLARD R. Single event effects: Mechanisms and classification[M]. NICOLAIDIS M. Soft Errors in Modern Electronic Systems. Boston: Springer, 2011: 27–54.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(4)  / Tables(2)

    Article Metrics

    Article views (798) PDF downloads(51) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return