High-performance Hardware Architecture Design and Implementation of Ed25519 Algorithm

Bin YU; Hai HUANG; Zhiwei LIU; Shilei ZHAO; Ning NA

doi:10.11999/JEIT200876

Volume 43 Issue 7

Jul. 2021

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Bin YU, Hai HUANG, Zhiwei LIU, Shilei ZHAO, Ning NA. High-performance Hardware Architecture Design and Implementation of Ed25519 Algorithm[J]. Journal of Electronics & Information Technology, 2021, 43(7): 1821-1827. doi: 10.11999/JEIT200876

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Bin YU, Hai HUANG, Zhiwei LIU, Shilei ZHAO, Ning NA. High-performance Hardware Architecture Design and Implementation of Ed25519 Algorithm[J]. Journal of Electronics & Information Technology, 2021, 43(7): 1821-1827. doi: 10.11999/JEIT200876

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High-performance Hardware Architecture Design and Implementation of Ed25519 Algorithm

doi: 10.11999/JEIT200876

School of Computer Science and Technology, Harbin University of Science and Technology, Harbin 150080, China

Funds: The Natural Science Foundation of Heilongjiang (YQ2019F010), Heilongjiang Postdoctoral Funds for Scientific Research Initiation (LBH-Q18065), The Science and Technology Development Special Project of Central Guide the Local Government of China (ZY20B11)

Received Date: 2020-10-12
Rev Recd Date: 2021-01-29

Available Online: 2021-03-01

Publish Date: 2021-07-10

Abstract

Abstract

The speed of existing signature and verification architecture is difficult to meet the requirement of the specific applications domain, to solve this problem a high-performance hardware architecture of Ed25519 algorithm is developed. The scalar multiplication algorithm is implemented by using the window method with 2 bit width to reduce the total cycle numbers of the algorithm significantly. By optimizing the order of operations of point addition and point doubling, the hardware utilization rate of multiplier is improved. The module multiplication is realized by using fast module reduction with low computational complexity, thus the overall operation speed is improved. The modular L algorithm based on Barrett reduction is proposed to reuse the fast modular reduction in scalar multiplications. By optimizing the modular power computation in the decompression process, the steps are simplified and the modular multiplication can be reused. Under the TSMC 55 nm CMOS process, the area of the proposed hardware architecture is 7.46×10⁵ equivalent gate, and the maximum frequency is up to 360 MHz. It can perform 9.06×10⁴ key generations, 8.82×10⁴ signatures and 3.99×10⁴ verifications per second.
- Elliptic Curve Digital Signature Algorithm (ECDSA),
- Edwards-curve,
- Hardware implementation,
- Scalar multiplication,
- Fast modular reduction

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References(19)

References

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