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Volume 43 Issue 12
Dec.  2021
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Jianjun LUO, Yifan SHEN, Di ZHOU, Chunyang FENG, Jiangxia DENG. High Performance Crypto Module with Array of Hardware Engines[J]. Journal of Electronics & Information Technology, 2021, 43(12): 3743-3748. doi: 10.11999/JEIT200855
Citation: Jianjun LUO, Yifan SHEN, Di ZHOU, Chunyang FENG, Jiangxia DENG. High Performance Crypto Module with Array of Hardware Engines[J]. Journal of Electronics & Information Technology, 2021, 43(12): 3743-3748. doi: 10.11999/JEIT200855

High Performance Crypto Module with Array of Hardware Engines

doi: 10.11999/JEIT200855
Funds:  The National Basic Research Program (JCKY2018415C001), Zhejiang Key Laboratory Foundation of Solid State Drive and Data Security (2015E10003)
  • Received Date: 2020-10-04
  • Rev Recd Date: 2021-09-30
  • Available Online: 2021-10-25
  • Publish Date: 2021-12-21
  • A high-performance crypto module prescribed in this paper offers advanced security solutions in big data applications. A module architecture, which consists of a high throughput interface, Central Manage & Monitor Module (CMMM) and multiple channels driving a group of crypto engines, is discussed here. CMMM distributes the tasks to the crypto engines and guides the data back to the host after processing by the dedicated algorithm. Since the module's performance is limited by the interface throughput and the scale of the crypto engines, an array with MMC/eMMC bus connections is built for PCIe high-speed interfaces. The more crypto engines are integrated into a system, the higher performance of this system can reach. To verify this architecture, an ASIC encryption card with PCIe Gen2×4 interface is made under semiconductor manufacturing process technology of 55 nm, and tested. The average throughput of this card can achieve up to 419.23 MB.
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