A Low-Cost Triple-Node-Upset-Resilient Latch Design

Zhengfeng HUANG; Xiandong LI; Peng CHEN; Qi XU; Tai Song; Haochen QI; Yiming OUYANG; Tianming NI

doi:10.11999/JEIT200379

Volume 43 Issue 9

Sep. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(9): 2508-2517

Zhengfeng HUANG, Xiandong LI, Peng CHEN, Qi XU, Tai Song, Haochen QI, Yiming OUYANG, Tianming NI. A Low-Cost Triple-Node-Upset-Resilient Latch Design[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2508-2517. doi: 10.11999/JEIT200379

Citation:

Zhengfeng HUANG, Xiandong LI, Peng CHEN, Qi XU, Tai Song, Haochen QI, Yiming OUYANG, Tianming NI. A Low-Cost Triple-Node-Upset-Resilient Latch Design[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2508-2517. doi: 10.11999/JEIT200379

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A Low-Cost Triple-Node-Upset-Resilient Latch Design

doi: 10.11999/JEIT200379

1.
School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230601, China
2.
School of Computer & Information, Hefei University of Technology, Hefei 230601, China
3.
School of Electrical Engineering, Anhui Polytechnic University, Wuhu 241000, China

Funds: The National Natural Science Foundation of China (61874156, 61874157, 61904001, 61904047), Anhui Province Natural Science Foundation (1908085QF272)

Received Date: 2020-05-05
Rev Recd Date: 2021-05-15

Available Online: 2021-08-11

Publish Date: 2021-09-16

Abstract

Abstract

As the feature size of integrated circuits continues to scale down, under the harsh radiation environment, the probability of single event triple node upsets in nano-scale CMOS integrated circuits is increasing, seriously affecting reliability. In order to realize the resilient of single-event triple-node-upsets, a Low-Cost Triple-Node-Upset-Resilient Latch (LC-TNURL) is proposed. The latch is composed of seven C-elements and seven clock-gating C-elements, and has a symmetrical ring-shaped cross-interlock structure. Using the interceptive characteristics of the C-elements and the cross-interlock connection mode, after any three internal nodes are flipped, the transient pulse propagates inside the latch. After the C-elements is blocked in multiple stages, it will disappear step by step to ensure the LC-TNURL latch can self-recover to the correct logic state. Detailed HSPICE simulation shows that the power consumption of the LC-TNURL latch is reduced by an average of 31.9%, the delay is reduced by an average of 87.8%, the power-delay product is reduced by an average of 92.3% and the area overhead is increased by an average of 15.4% compared to other triple-node-upsets hardened latches (TNU-Latch, LCTNUT, TNUTL, TNURL). The LC-TNURL latch proposed in this paper is the least sensitive to PVT fluctuations and has high reliability compared with reference latches.
- Latch,
- Radiation hardening by design,
- C-elements,
- Resilient,
- Triple node upsets

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References(25)

References

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