Research on Automatic Mapping Method of Reconfigurable Block Cipher Instruction Set Processor

Sheng LI; Zibin DAI

doi:10.11999/JEIT200372

Volume 43 Issue 9

Sep. 2021

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Sheng LI, Zibin DAI. Research on Automatic Mapping Method of Reconfigurable Block Cipher Instruction Set Processor[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2526-2533. doi: 10.11999/JEIT200372

Citation:

Sheng LI, Zibin DAI. Research on Automatic Mapping Method of Reconfigurable Block Cipher Instruction Set Processor[J]. Journal of Electronics & Information Technology, 2021, 43(9): 2526-2533. doi: 10.11999/JEIT200372

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Research on Automatic Mapping Method of Reconfigurable Block Cipher Instruction Set Processor

doi: 10.11999/JEIT200372 cstr: 32379.14.JEIT200372

Sheng LI^{1, 2
,
,},
Zibin DAI¹

1.
The PLA Information Engineering University, Zhengzhou 450001, China
2.
Railway Police College, Zhengzhou 450053, China

Received Date: 2020-05-12
Rev Recd Date: 2021-01-12

Available Online: 2021-02-02

Publish Date: 2021-09-16

Abstract

Abstract

The allocation of computing resources and register resources is an important issue for automatic parallel mapping of reconfigurable processors. In this paper, for the resource allocation of reconfigurable block cipher instruction set processors, an operator scheduling parameter model and processor resource parameter model are established, and the constraint relationship between the parallel scheduling of block ciphers and resource consumption is studied; Consequently, an automatic mapping algorithm based on greedy thinking, list scheduling and linear scanning is proposed to realize the block cipher atuomatic mapping on the reconfigurable block cipher instruction set processor. The experiment verifies the effect of the algorithm’s parallel scheduling under different resource constraints, and the contrast of AES-128 algorithm’s mapping effect is made to verify the progress of the algorithm, which obtains certain significance for the parallel computing research of block ciphers in reconfigurable processing.
- Reconfigurable block cipher instruction set processor,
- Automatic mapping,
- Resource allocation,
- List scheduling,
- Linear scan

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References(17)

References

[1]	WU L, WEAVER C, and AUSTIN T. CryptoManiac: A fast flexible architecture for secure communication[C]. The 28th Annual International Symposium on Computer Architecture, Goteborg, Sweden, 2001: 110–119. doi: 10.1109/ISCA.2001.937439.
[2]	孟涛, 戴紫彬. 分组密码处理器的可重构分簇式架构[J]. 电子与信息学报, 2009, 31(2): 453–456. doi: 10.3724/SP.J.1146.2007.01586 MENG Tao and DAI Zibin. Reconfigurable clustered architecture of block cipher processor[J]. Journal of Electronics &Information Technology, 2009, 31(2): 453–456. doi: 10.3724/SP.J.1146.2007.01586
[3]	BUCHTY R, HEINTZE N, and OLIVA D. Cryptonite–a programmable crypto processor architecture for high-bandwidth applications[C]. The International Conference on Architecture of Computing Systems, Augsburg, Germany, 2004: 184–198. doi: 10.1007/978-3-540-24714-2_15.
[4]	LI Wei, ZENG Xiaoyang, NAN Longmei, et al. A reconfigurable block cryptographic processor based on VLIW architecture[J]. China Communication, 2016, 13(1): 91–99. doi: 10.1109/CC.2016.7405707
[5]	严迎建, 王寿成, 徐进辉, 等. 基于Amdahl定律的分组密码并行处理模型研究[J]. 北京理工大学学报, 2018, 38(9): 977–984. doi: 10.15918/j.tbit1001-0645.2018.09.017 YAN Yingjian, WANG Shoucheng, XU Jinhui, et al. Research on parallel processing model for block cipher based on Amdahl’s law[J]. Transactions of Beijing Institute of Technology, 2018, 38(9): 977–984. doi: 10.15918/j.tbit1001-0645.2018.09.017
[6]	刘雷波, 王博, 魏少军. 可重构计算密码处理器[M]. 北京: 科学出版社, 2019: 167–172. LIU Leibo, WANG Bo, and WEI Shaojun. Reconfigurable Cryptographic Processor[M]. Beijing: Scientific Publisher, 2019: 167–172.
[7]	戴紫彬, 曲彤洲. 基于预配置和配置重用的粗粒度动态可重构系统任务调度技术[J]. 电子与信息学报, 2019, 41(6): 1458–1465. doi: 10.11999/JEIT180831 DAI Zibin and QU Tongzhou. Task scheduling technology for coarse-grained dynamic reconfigurable system based on configuration prefetching and reuse[J]. Journal of Electronics &Information Technology, 2019, 41(6): 1458–1465. doi: 10.11999/JEIT180831
[8]	杜怡然, 南龙梅, 戴紫彬, 等. 可重构分组密码逻辑阵列加权度量模型及高能效映射算法[J]. 电子学报, 2019, 47(1): 82–91. doi: 10.3969/j.issn.0372-2112.2019.01.011 DU Yiran, NAN Longmei, DAI Zibin, et al. Reconfigurable block cryptographic logic array weighted metric model and high energy-efficient mapping algorithm[J]. Acta Electronica Sinica, 2019, 47(1): 82–91. doi: 10.3969/j.issn.0372-2112.2019.01.011
[9]	杜怡然, 杨萱, 戴紫彬, 等. 粗粒度可重构密码逻辑阵列智能映射算法研究[J]. 电子学报, 2020, 48(1): 101–109. doi: 10.3969/j.issn.0372-2112.2020.01.012 DU Yiran, YANG Xuan, DAI Zibin, et al. Research on coarse-grained reconfigurable cryptographic logic array intelligent mapping algorithm[J]. Acta Electronica Sinica, 2020, 48(1): 101–109. doi: 10.3969/j.issn.0372-2112.2020.01.012
[10]	LIU Dajiang, YIN Shouyi, LUO Guojie, et al. Data-flow graph mapping optimization for CGRA with deep reinforcement learning[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38(12): 2271–2283. doi: 10.1109/TCAD.2018.2878183
[11]	LI Wei, ZENG Xiaoyang, DAI Zibin, et al. A high energy-efficient reconfigurable VLIW symmetric cryptographic processor with loop buffer structure and chain processing mechanism[J]. Chinese Journal of Electronics, 2017, 26(6): 1161–1167. doi: 10.1049/cje.2017.06.010
[12]	王寿成, 严迎建, 徐进辉. 基于流体系结构的高效能分组密码处理器研究[J]. 电子学报, 2017, 45(4): 937–943. doi: 10.3969/j.issn.0372-2112 WANG Shoucheng, YAN Yingjian, and XU Jinhui. Research of high-efficient block cipher processor based on stream architecture[J]. Acta Electronica Sinica, 2017, 45(4): 937–943. doi: 10.3969/j.issn.0372-2112
[13]	张惠臻, 王超, 李曦, 等. 可重构指令集处理器的代码优化生成算法研究[J]. 计算机研究与发展, 2012, 49(9): 2018–2026. ZHANG Huizhen, WANG Chao, LI Xi, et al. An optimized code-generating algorithm for reconfigurable instruction set processors[J]. Journal of Computer Research and Development, 2012, 49(9): 2018–2026.
[14]	KWOK Y K and AHMAD I. Static scheduling algorithms for allocating directed task graphs to multiprocessors[J]. ACM Computing Surveys, 1999, 31(4): 406–471. doi: 10.1145/344588.344618
[15]	DU Yiran, LI Wei, DAI Zibin, et al. PVHArray: An energy-efficient reconfigurable cryptographic logic array with intelligent mapping[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(5): 1302–1315. doi: 10.1109/tvlsi.2020.2972392
[16]	LIU Bin and BAAS B M. Parallel AES encryption engines for many-core processor arrays[J]. IEEE Transactions on Computers, 2013, 62(3): 536–547. doi: 10.1109/TC.2011.251
[17]	SHAN Weiwei, FU Xingyuan, and XU Zhipeng. A secure reconfigurable crypto IC with countermeasures against SPA, DPA, and EMA[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(7): 1201–1205. doi: 10.1109/TCAD.2015.2419621