Design and Hardware Implementation of Image Recognition System Based on Improved Neural Network

Dong WEI; Bochen DONG; Yiqing LIU

doi:10.11999/JEIT200202

Volume 43 Issue 7

Jul. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(7): 1828-1833

Dong WEI, Bochen DONG, Yiqing LIU. Design and Hardware Implementation of Image Recognition System Based on Improved Neural Network[J]. Journal of Electronics & Information Technology, 2021, 43(7): 1828-1833. doi: 10.11999/JEIT200202

Citation:

Dong WEI, Bochen DONG, Yiqing LIU. Design and Hardware Implementation of Image Recognition System Based on Improved Neural Network[J]. Journal of Electronics & Information Technology, 2021, 43(7): 1828-1833. doi: 10.11999/JEIT200202

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Design and Hardware Implementation of Image Recognition System Based on Improved Neural Network

doi: 10.11999/JEIT200202

Dong WEI^{1, 2
,
,},
Bochen DONG¹,
Yiqing LIU³

1.
School of Electrical and Information Engineering, Beijing University of Civil Engineering and Architecture, Beijing 100044, China
2.
Beijing Key Laboratory of Intelligent Processing for Building Big Data, Beijing Municipal Science and Technology Commission, Beijing 100044, China
3.
Beijing Yading Intelligent Technology Limited Company, Beijing 100071, China

Funds: The High Level Innovation Team Construction Project of Beijing Municipal Universities (IDHT20190506), The National Natural Science Foundation of China (61871020), The Key Science and Technology Plan Project of Beijing Municipal Education Commission of China (KZ201810016019)

Received Date: 2020-03-24
Rev Recd Date: 2020-09-23

Available Online: 2020-12-09

Publish Date: 2021-07-10

Abstract

Abstract

To solve the problem that most existing image recognition systems are implemented in software which can not utilize the parallel computing power of neural networks, this paper proposes a FPGA image recognition system based on improved RBF neural network hardware. The multiplication operation in the neural networks is complex and inconvenient for hardware implementation. Furthermore, a sort circuit based on bit comparison is designed to solve the problem of fast sorting of a large number of data. Then, a multi-target image recognition application system is developed. The feature extraction part in the developed system is implemented by FPGA, and the image recognition part is implemented by ASIC circuit. The experimental results show that the average recognition time of the improved RBF neural network algorithm proposed is 50% shorter than that of LeNet-5, AlexNet and VGG16, and the time for the developed hardware system to recognize 10000 sample pictures is 165μs, which is reduced by about 60% compared with 426.6μs required by a DSP chip system.
- FPGA,
- ASIC circuit,
- RBF neural networks,
- Image recognition system

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References(11)

References

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