Rollback Cyclic Redundancy Check Algorithm in High Bit-width

Yu LUO; Jiasong GUO

doi:10.11999/JEIT200141

Volume 43 Issue 4

Apr. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(4): 1057-1063

Yu LUO, Jiasong GUO. Rollback Cyclic Redundancy Check Algorithm in High Bit-width[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1057-1063. doi: 10.11999/JEIT200141

Citation:

Yu LUO, Jiasong GUO. Rollback Cyclic Redundancy Check Algorithm in High Bit-width[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1057-1063. doi: 10.11999/JEIT200141

Yu LUO, Jiasong GUO. Rollback Cyclic Redundancy Check Algorithm in High Bit-width[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1057-1063. doi: 10.11999/JEIT200141

Citation:

Yu LUO, Jiasong GUO. Rollback Cyclic Redundancy Check Algorithm in High Bit-width[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1057-1063. doi: 10.11999/JEIT200141

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Rollback Cyclic Redundancy Check Algorithm in High Bit-width

doi: 10.11999/JEIT200141

Yu LUO^{1
,
,},
Jiasong GUO²

1.
School of Economics and Management; Beijing Jiaotong University, Beijing 100044, China
2.
Department of Retirement, Beijing Jiaotong University, Beijing 100044, China

Received Date: 2020-03-03
Rev Recd Date: 2020-06-13

Available Online: 2020-07-16

Publish Date: 2021-04-20

Abstract

Abstract

In order to overcome the complicated implementation to process tail data in high bit-width Cyclic Redundancy Check(CRC) calculation for variable length packet, linear matrix computation is used to investigate CRC inverse calculation. And a rollback algorithm is introduced to simplify the regular algorithm. Then the experiment is conducted to implement the rollback algorithm in Altera FPGA device. The results show that rollback algorithm utilizes fewer resource and is more easily to implement. In 512 bit data width variable length CRC calculation implement in FPGA, the resource utilization is decreased to 15% of regular algorithm by applying rollback algorithm. Synthesis time is decreased to 30%, and Place&Route time is deceased to 40%. It is concluded that the new rollback algorithm has great advantage.
- Cyclic Redundancy Check(CRC),
- FPGA,
- Matrix linear computation,
- Rollback

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References(17)

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