Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions

Jing KANG; Junshe AN; Bingbing WANG

doi:10.11999/JEIT200118

Volume 43 Issue 12

Dec. 2021

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Article Navigation > Journal of Electronics & Information Technology > 2021 > 43(12): 3727-3734

Jing KANG, Junshe AN, Bingbing WANG. Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions[J]. Journal of Electronics & Information Technology, 2021, 43(12): 3727-3734. doi: 10.11999/JEIT200118

Citation:

Jing KANG, Junshe AN, Bingbing WANG. Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions[J]. Journal of Electronics & Information Technology, 2021, 43(12): 3727-3734. doi: 10.11999/JEIT200118

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Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions

doi: 10.11999/JEIT200118

Jing KANG^{1, 2
,
,},
Junshe AN¹,
Bingbing WANG^{1, 2}

1.
National Space Science Center, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China

Funds: The Space Science Leading Satellite Project, Chinese Academy of Sciences(XDA15320100)

Received Date: 2020-02-21
Rev Recd Date: 2021-06-07

Available Online: 2021-07-12

Publish Date: 2021-12-21

Abstract

Abstract

A new low complexity and reconfigurable Low Density Parity Check (LDPC) encoder design based on the Consultative Committee for Space Data Systems (CCSDS) standard is proposed to meet the high throughput, low latency and high reliability requirement for high-speed satellite-to-ground data transmission systems of Low Earth Orbit (LEO). This design is parallel reconfigurable by inserting 0 into information bits and splitting cyclic matrices, and analyzed the structural characteristics of different parallelism encoding. Benefitting from the parallel reconfiguration, the throughput is increased and the flexibility is guaranteed. Furthermore, using optimized shift register adder accumulators can reduce the hardware resources. The proposed encoder design is implemented on Xilinx FPGA. The experimental results show that the maximum encoding speed is up to 1 Gbps @125 MHz, and the normalized throughput is increased by 17.1% compared with the similar parallel encoder. And resources of registers and look-up tables are reduced by 13.7% and 14.8% respectively, compared with the existing encoder.
- High-speed satellite-to-ground data transmissions,
- Low Density Parity Check (LDPC),
- Reconfigurable,
- Low complexity,
- FPGA

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References(16)

References

[1]	李炯卉. 基于可变编码多载波调制技术的星地高速数传系统研究[D]. [博士论文], 中国科学院大学(中国科学院国家空间科学中心), 2018. LI Jionghui. Satellite-ground high-rate data transmission system based on variable coding multi-carrier modulation[D].[Ph.D. dissertation], University of Chinese Academy of Sciences (National Space Science Center, the Chinese Academy of Sciences), 2018.
[2]	张浩, 殷柳国. 星地高速数传系统LDPC编码器ASIC集成芯片设计[J]. 宇航学报, 2015, 36(1): 96–102. doi: 10.3873/j.issn.1000-1328.2015.01.013 ZHANG Hao and YIN Liuguo. ASIC design of an LDPC encoder for satellite-ground high-speed data transmission system[J]. Journal of Astronautics, 2015, 36(1): 96–102. doi: 10.3873/j.issn.1000-1328.2015.01.013
[3]	GALLAGER R. Low-density parity-check codes[J]. IRE Transactions on Information Theory, 1962, 8(1): 21–28. doi: 10.1109/TIT.1962.1057683
[4]	CCSDS. CCSDS 131.0-B-2-TM Synchronization and channel coding[S]. Washington: CCSDS, 2011.
[5]	WU Hao and WANG Huayong. A high throughput implementation of QC-LDPC codes for 5G NR[J]. IEEE Access, 2019, 7: 185373–185384. doi: 10.1109/ACCESS.2019.2960839
[6]	MAHDI A and PALIOURAS V. A low complexity-high throughput QC-LDPC encoder[J]. IEEE Transactions on Signal Processing, 2014, 62(10): 2696–2708. doi: 10.1109/tsp.2014.2314435
[7]	马明晓, 安军社. 欧氏几何LDPC长码的卫星通信编码方案研究[J]. 计算机测量与控制, 2014, 22(3): 813–815, 829. doi: 10.16526/j.cnki.11-4762/tp.2014.03.051 MA Mingxiao and AN Junshe. Research on long Euclidean geometry-based LDPC coding scheme for satellite communications[J]. Computer measurement &Control, 2014, 22(3): 813–815, 829. doi: 10.16526/j.cnki.11-4762/tp.2014.03.051
[8]	燕威, 薛长斌. 高效低功耗低并行度LDPC编码方法[J]. 电子与信息学报, 2016, 38(9): 2268–2273. doi: 10.11999/JEIT151362 YAN Wei and XUE Changbin. An efficient LDPC encoder scheme with low-power low-parallel[J]. Journal of Electronics &Information Technology, 2016, 38(9): 2268–2273. doi: 10.11999/JEIT151362
[9]	WANG Zhaohui, HAO Xin, LIN Changxing, et al. An efficient hardware LDPC encoder based on partial parallel structure for CCSDS[C]. The IEEE 18th International Conference on Communication Technology, Chongqing, China, 2018: 136–139.
[10]	叶荣润, 黄聪, 俞帆. 高速并行LDPC编码的FPGA实现[J]. 无线电工程, 2012, 42(3): 25–26, 37. doi: 10.3969/j.issn.1003-3106.2012.03.008 YE Rongrun, HUANG Cong, and YU Fan. FPGA implementation of high-speed parallel LDPC encoding[J]. Radio Engineering, 2012, 42(3): 25–26, 37. doi: 10.3969/j.issn.1003-3106.2012.03.008
[11]	曹明星. 卫星通信中LDPC码高速编译码器实现技术研究[D].[硕士论文], 西安电子科技大学, 2018. CAO Mingxing. Implementation of high-speed codec for LDPC codes in satellite communication[D].[Master dissertation], Xidian University, 2018.
[12]	王干. 800 Mbps吞吐率LDPC码并行编译码关键技术与验证[D]. [硕士论文], 电子科技大学, 2017. WANG Gan. Key technology and verification of 800Mbps throughput parallel coding and decoding for LDPC code[D]. [Master dissertation], University of Electronic Science and Technology of China, 2017.
[13]	栾志斌, 裴玉奎, 葛宁. 低存储高速可重构LDPC码译码器设计及ASIC实现[J]. 电子与信息学报, 2014, 36(10): 2287–2292. doi: 10.3724/SP.J.1146.2013.01939 LUAN Zhibin, PEI Yukui, and GE Ning. Design and ASIC implementation of low memory high throughput reconfigurable LDPC decoder[J]. Journal of Electronics &Information Technology, 2014, 36(10): 2287–2292. doi: 10.3724/SP.J.1146.2013.01939
[14]	魏星, 黄志洪, 杨海钢. 高吞吐率双模浮点可重构FFT处理器设计实现[J]. 电子与信息学报, 2018, 40(12): 3042–3050. doi: 10.11999/JEIT180170 WEI Xing, HUANG Zhihong, and YANG Haigang. High throughput dual-mode reconfigurable floating-point FFT processor[J]. Journal of Electronics &Information Technology, 2018, 40(12): 3042–3050. doi: 10.11999/JEIT180170
[15]	王刚, 李冰, 刘勇, 等. 一种可重构LDPC编码器的设计与实现[J]. 微计算机信息, 2010, 26(12-2): 168–170. doi: 10.3969/j.issn.2095-6835.2010.35.067 WANG Gang, LI Bing, LIU Yong, et al. Design and implementation of a reconfigurable LDPC encoder[J]. Microcomputer Information, 2010, 26(12-2): 168–170. doi: 10.3969/j.issn.2095-6835.2010.35.067
[16]	袁东风, 张海刚. LDPC码理论与应用[M]. 北京: 人民邮电出版社, 2008: 37–40. YUAN Dongfeng and ZHANG Haigang. LDPC Code Theory and Applications[M]. Beijing: Post & Telecom Press, 2008: 37–40.