On the Implementation of 5G LDPC Decoder

Dongwei HU

doi:10.11999/JEIT200046

Volume 43 Issue 4

Apr. 2021

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Dongwei HU. On the Implementation of 5G LDPC Decoder[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1112-1119. doi: 10.11999/JEIT200046

Citation:

Dongwei HU. On the Implementation of 5G LDPC Decoder[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1112-1119. doi: 10.11999/JEIT200046

Dongwei HU. On the Implementation of 5G LDPC Decoder[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1112-1119. doi: 10.11999/JEIT200046

Citation:

Dongwei HU. On the Implementation of 5G LDPC Decoder[J]. Journal of Electronics & Information Technology, 2021, 43(4): 1112-1119. doi: 10.11999/JEIT200046

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On the Implementation of 5G LDPC Decoder

doi: 10.11999/JEIT200046

Dongwei HU^,

54th Institute of CETC, Shijiazhuang 050080, China

Received Date: 2020-01-13
Rev Recd Date: 2020-07-11

Available Online: 2020-07-24

Publish Date: 2021-04-20

Abstract

Abstract

This paper focuses on the Low-Density-Parity-Check (LDPC) decoder for 5G New Radio (NR) specification. After introducing the characteristics of the LDPC code in 5G NR, the performance of different decoding algorithms are compared, and then the overall architecture of the decoder is proposed. In the proposed architecture, the decoder is divided into high-speed decoder and high-performance decoder. The high-speed decoder is intended for high-rate and high throughput decoding, while the high-performance decoder is used for low-rate decoding under low Signal-to-Noise-Ratio (SNR) scenarios, which is for communications under extremely bad situations, and does not need a high throughput. The design is implemented on Field Programmable Gate Array (FPGA) and the results are shown.
- 5G Mobile Communications,
- LDPC,
- Decoder,
- Field Programmable Gate Array (FPGA)

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References(18)

References

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