4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC

Yan XUE; Zongguang YU; Zhenhai CHEN; Jinghe WEI; Hongwen QIAN

doi:10.11999/JEIT190592

Volume 42 Issue 9

Sep. 2020

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Article Navigation > Journal of Electronics & Information Technology > 2020 > 42(9): 2312-2318

Yan XUE, Zongguang YU, Zhenhai CHEN, Jinghe WEI, Hongwen QIAN. 4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC[J]. Journal of Electronics & Information Technology, 2020, 42(9): 2312-2318. doi: 10.11999/JEIT190592

Citation:

Yan XUE, Zongguang YU, Zhenhai CHEN, Jinghe WEI, Hongwen QIAN. 4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC[J]. Journal of Electronics & Information Technology, 2020, 42(9): 2312-2318. doi: 10.11999/JEIT190592

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4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC

doi: 10.11999/JEIT190592

Yan XUE¹,
Zongguang YU^{1
,
,},
Zhenhai CHEN^{1, 2, 3},
Jinghe WEI¹,
Hongwen QIAN¹

1.
No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
2.
School of Information Engineering, Huangshan University, Huangshan 245041, China
3.
Engineering Technology Research Center of Intelligent Microsystems AnHui Province, Huangshan 245041, China

Received Date: 2019-08-06
Rev Recd Date: 2020-08-06

Available Online: 2020-08-12

Publish Date: 2020-09-27

Abstract

Abstract

A 4.5 bit sub-stage circuit for high speed high precision charge domain pipelined Analog-to-Digital Converter (ADC) is proposed. Instead of the high-performance opamps used in traditional switched-capacitor pipelined ADCs, charge transfer and residue charge calculation is realized with Boosted Charge Transfer (BCT) circuit in the proposed 4.5 bit sub-stage. Therefore, the power consumption of the 4.5 bit sub-stage circuit can be reduced remarkably. The proposed 4.5 bit sub-stage circuit is used as the 1st stage circuit for a 14 bit 210 MS/s charge domain pipelined ADC and realized in a 1P6M 0.18 μm CMOS process. Test results show the 14 bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dB, with 30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm².
- Pipelined Analog-to-Digital Converter(ADC),
- Charge-domain,
- Sub-stage circuit,
- Low power

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References(15)

References

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