Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm

Rong CHEN; Lan CHEN; Arfan Haider WAHLA

doi:10.11999/JEIT190503

Volume 42 Issue 5

Jun. 2020

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Article Navigation > Journal of Electronics & Information Technology > 2020 > 42(5): 1261-1267

Rong CHEN, Lan CHEN, Arfan Haider WAHLA. Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm[J]. Journal of Electronics & Information Technology, 2020, 42(5): 1261-1267. doi: 10.11999/JEIT190503

Citation:

Rong CHEN, Lan CHEN, Arfan Haider WAHLA. Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm[J]. Journal of Electronics & Information Technology, 2020, 42(5): 1261-1267. doi: 10.11999/JEIT190503

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Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm

doi: 10.11999/JEIT190503

Rong CHEN^{1, 2, 3},
Lan CHEN^{1, 3
,
,},
Arfan Haider WAHLA^{1, 2, 3}

1.
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China
3.
Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology, Beijing 100029, China

Funds: The National Science and Technology Major Project (2018ZX03001006-002)

Received Date: 2019-07-15
Rev Recd Date: 2019-10-30

Available Online: 2019-11-07

Publish Date: 2020-06-04

Abstract

Abstract

Cyclic Redundancy Check (CRC) is used in cascade with channel coding to improve the convergence of the decoding. In the new generation of wireless communication systems, such as 5G, both code length and code rate are diverse. To improve the decoding efficiency of cascaded systems, a CRC parallel algorithm with variable computing width is proposed in this paper. Based on the existing fixed bit-width parallel algorithm, this algorithm combines the parallel calculation of feedback data and input data in the formula recursive method, realizing a highly parallel CRC check architecture with variable bit-width CRC calculation. Compared with the existing parallel algorithms, the merged algorithm saves the overhead of circuit resources. When the bit-width is fixed, the resource saving effect is obvious, and at the same time, the feedback delay is also optimized by nearly 50%. When the bit-width is variable, the use of resources is also optimized accordingly.
- Cyclic Redundancy Check(CRC),
- Parallel algorithm,
- Formula recursion algorithm

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References(17)

References

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