Research on Efficient FPGA Bitstream Generation System Based on Mode Matching and Hierarchical Mapping

Kaihui TU; Zhihong HUANG; Zhengrong HOU; Haigang YANG

doi:10.11999/JEIT190143

Volume 41 Issue 11

Nov. 2019

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Article Navigation > Journal of Electronics & Information Technology > 2019 > 41(11): 2585-2591

Kaihui TU, Zhihong HUANG, Zhengrong HOU, Haigang YANG. Research on Efficient FPGA Bitstream Generation System Based on Mode Matching and Hierarchical Mapping[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2585-2591. doi: 10.11999/JEIT190143

Citation:

Kaihui TU, Zhihong HUANG, Zhengrong HOU, Haigang YANG. Research on Efficient FPGA Bitstream Generation System Based on Mode Matching and Hierarchical Mapping[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2585-2591. doi: 10.11999/JEIT190143

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Research on Efficient FPGA Bitstream Generation System Based on Mode Matching and Hierarchical Mapping

doi: 10.11999/JEIT190143

1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China

Funds: The National Natural Science Foundation of China (61876172, 61704173), The Major Program of Beijing Science and Technology (Z171100000117019)

Received Date: 2019-03-12
Rev Recd Date: 2019-05-30

Available Online: 2019-06-04

Publish Date: 2019-11-01

Abstract

Abstract

Bitstream generator in FPGA Electronic Design Automation(EDA) offers precise configuration information, which enables the application circuits to be implemented on the target device. On one hand, modern FPGAs tend to have larger device scale and more configuration bits, on the other hand, embedded applications (e.g. eFPGAs) require better configuration efficiency and smaller, more adaptive database. In order to meet these new requirements, a bit-stream generation method is proposed which firstly models the configurable resources by configuration modes and matches the netlist with these models, then hierarchical mapping strategy is used to search every bit on a dynamically generated database determined by the array floorplan. This method well meets the challenges that embedded applications may bring-the surge of configuration bit count and the changeable size of the array. Compared to flattened modelling and mapping method, its time complexity is reduced from O(n) to O(lgn).
- FPGA,
- Bitstream generation,
- Embedded,
- Configuration mode,
- Hierarchy

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References(18)

References

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