A Circuit Optimization Method of Improved Lookup Table for Highly Efficient Resource Utilization

Lijiang GAO; Haigang YANG; Wei LI; Yanan HAO; Changlong LIU; Caixia SHI

doi:10.11999/JEIT190095

Volume 41 Issue 10

Oct. 2019

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Article Navigation > Journal of Electronics & Information Technology > 2019 > 41(10): 2382-2388

Lijiang GAO, Haigang YANG, Wei LI, Yanan HAO, Changlong LIU, Caixia SHI. A Circuit Optimization Method of Improved Lookup Table for Highly Efficient Resource Utilization[J]. Journal of Electronics & Information Technology, 2019, 41(10): 2382-2388. doi: 10.11999/JEIT190095

Citation:

Lijiang GAO, Haigang YANG, Wei LI, Yanan HAO, Changlong LIU, Caixia SHI. A Circuit Optimization Method of Improved Lookup Table for Highly Efficient Resource Utilization[J]. Journal of Electronics & Information Technology, 2019, 41(10): 2382-2388. doi: 10.11999/JEIT190095

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A Circuit Optimization Method of Improved Lookup Table for Highly Efficient Resource Utilization

doi: 10.11999/JEIT190095

Lijiang GAO^{1, 2},
Haigang YANG^{1, 2
,
,},
Wei LI³,
Yanan HAO⁴,
Changlong LIU⁴,
Caixia SHI¹

1.
Institure of Electronics, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China
3.
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
4.
The 54th Research Institute of CETC, Shijiazhuang 050081, China

Received Date: 2019-02-17
Rev Recd Date: 2019-04-12

Available Online: 2019-04-25

Publish Date: 2019-10-01

Abstract

Abstract

The circuit structure optimization method for Basic programmable Logic Element (BLE) of FPGA is studied. Considering finding the solution to the bottleneck problem of low resource utilization efficiency in logic and arithmetic operations with 4-input Look Up Table (LUT), some efforts to improve BLE design based on 4-input LUT are explored. A high area-efficient LUT structure is proposed, and the possible benefits of such a new structure are analyzed theoretically and simulated. Further, a statistical method for evaluation of the post synthesis and mapping netlist is also proposed. Finally, a number of experiments are carried out to assess the proposed structure based on the MCNC and VTR benchmarks. The results show that, compared with Intel Stratix series FPGAs, the optimized structure proposed in this paper improves respectively the area efficiency of the FPGA by 10.428% and 10.433% in average under the MCNC and VTR benchmark circuits.
- Basic programmable Logic Element (BLE),
- Look Up Table (LUT),
- Carry chain,
- Mapping,
- Packing

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References(15)

References

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