Optimization Algorithm of Dual-port Memory Mapping on FPGA

Yu XU; Yu LIN; Haigang YANG

doi:10.11999/JEIT190077

Volume 42 Issue 10

Oct. 2020

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Article Navigation > Journal of Electronics & Information Technology > 2020 > 42(10): 2549-2556

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Yu XU, Yu LIN, Haigang YANG. Optimization Algorithm of Dual-port Memory Mapping on FPGA[J]. Journal of Electronics & Information Technology, 2020, 42(10): 2549-2556. doi: 10.11999/JEIT190077

Citation:

Yu XU, Yu LIN, Haigang YANG. Optimization Algorithm of Dual-port Memory Mapping on FPGA[J]. Journal of Electronics & Information Technology, 2020, 42(10): 2549-2556. doi: 10.11999/JEIT190077

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Optimization Algorithm of Dual-port Memory Mapping on FPGA

doi: 10.11999/JEIT190077

Yu XU^{1, 2},
Yu LIN³,
Haigang YANG^{1, 2
,
,}

1.
Institute of Electrics, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China
3.
Xilinx Incorporated, Beijing 100101, China

Funds: The National Natural Science Foundation of China (61474120, 61404140, 61704173)

Received Date: 2019-01-28
Rev Recd Date: 2020-01-20

Available Online: 2020-07-20

Publish Date: 2020-10-13

Abstract

Abstract

FPGA memory mapping algorithm utilizes distributed storage resources on chip and cooperates with some auxiliary circuits to realize the different needs of users in designing logical storage functions. Previous studies on dual-port memory mapping algorithm are relatively few. There is still much space for improvement in the mapping results by mature commercial EDA tools. An optimization algorithm of dual-port memory mapping is proposed for area, delay and power consumption, and a specific configuration scheme is given. Experiments show that when facing simple storage requirements, the mapping results are consistent with those of commercial tools; when facing complex storage requirements, the mapping results of area optimization and power optimization are improved by at least 50% compared with commercial tools Vivado.
- FPGA,
- Dual-port memory mapping,
- Delay optimization,
- Area optimization,
- Power optimization

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References(15)

References

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