Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA

Huabiao QIN; Qinping CAO

doi:10.11999/JEIT190058

Volume 41 Issue 11

Nov. 2019

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Huabiao QIN, Qinping CAO. Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2599-2605. doi: 10.11999/JEIT190058

Citation:

Huabiao QIN, Qinping CAO. Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2599-2605. doi: 10.11999/JEIT190058

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Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA

doi: 10.11999/JEIT190058

Huabiao QIN^,,
Qinping CAO

School of Electronics and Information Engineering, South China University of Technology, Guangzhou 510641, China

Funds: The Science and Technology Project of Guangdong Provience (2014B090910002)

Received Date: 2019-01-22
Rev Recd Date: 2019-06-10

Available Online: 2019-06-20

Publish Date: 2019-11-01

Abstract

Abstract

Considering the large computational complexity and the long-time calculation of Convolutional Neural Networks (CNN), an Field-Programmable Gate Array(FPGA)-based CNN hardware accelerator is proposed. Firstly, by deeply analyzing the forward computing principle and exploring the parallelism of convolutional layer, a hardware architecture in which parallel for the input channel and output channel, deep pipeline for the convolution window is presented. Then, a full parallel multi-addition tree is designed to accelerate convolution and efficient window buffer to implement deep pipelining operation of convolution window. The experimental results show that the energy efficiency ratio of proposed accelerator reaches 32.73 GOPS/W, which is 34% higher than the existing solutions, as the performance reaches 317.86 GOPS.
- Convolutional Neural Networks (CNN),
- Hardware acceleration,
- FPGA,
- Parallel computation,
- Deep pipeline

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References(12)

References

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