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Volume 41 Issue 10
Oct.  2019
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Lijiang GAO, Haigang YANG, Chao ZHANG. Research into Low Thermal Gradient Oriented 3D FPGA Interconnect Channel Architecture Design[J]. Journal of Electronics & Information Technology, 2019, 41(10): 2389-2395. doi: 10.11999/JEIT181134
Citation: Lijiang GAO, Haigang YANG, Chao ZHANG. Research into Low Thermal Gradient Oriented 3D FPGA Interconnect Channel Architecture Design[J]. Journal of Electronics & Information Technology, 2019, 41(10): 2389-2395. doi: 10.11999/JEIT181134

Research into Low Thermal Gradient Oriented 3D FPGA Interconnect Channel Architecture Design

doi: 10.11999/JEIT181134
Funds:  The National Natural Science Foundation of China (61876172, 61704173), The Major Program of Beijing Science and Technology (Z171100000117019)
  • Received Date: 2018-12-10
  • Rev Recd Date: 2019-03-18
  • Available Online: 2019-04-13
  • Publish Date: 2019-10-01
  • To solve the problem of heat dissipation in Three Dimensional Field Programmable Gate Array Technology (3D FPGA), an interconnect channel architectural design method with low thermal gradient feature is proposed. A thermal resistance network model is established for the 3D FPGA, and theoretical studies and thermal simulation experiments are carried out on the influence of different types of channels on the thermal performance of 3D FPGA. Further, non-uniform vertical direction channel structures of 3D FPGA are proposed. Experiments indicate that 3D FPGA designed using the method proposed can reduce the maximum temperature gradient between different layers by 76.8% and the temperature gradient within the same layer by 10.4% compared with the traditional channel structure of 3D FPGA.
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