A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors

Hejiu ZHANG; Ningmei YU; Nan LÜ; Ga LIU

doi:10.11999/JEIT180752

Volume 41 Issue 6

Jun. 2019

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Article Navigation > Journal of Electronics & Information Technology > 2019 > 41(6): 1466-1471

Hejiu ZHANG, Ningmei YU, Nan LÜ, Ga LIU. A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors[J]. Journal of Electronics & Information Technology, 2019, 41(6): 1466-1471. doi: 10.11999/JEIT180752

Citation:

Hejiu ZHANG, Ningmei YU, Nan LÜ, Ga LIU. A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors[J]. Journal of Electronics & Information Technology, 2019, 41(6): 1466-1471. doi: 10.11999/JEIT180752

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A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors

doi: 10.11999/JEIT180752

Hejiu ZHANG¹,
Ningmei YU^{1
,
,},
Nan LÜ²,
Ga LIU¹

1.
School of Automation and Information Engineering, Xi’an University of Technology, Xi’an 710048, China
2.
School of Information Technology and Equipment Engineering, Xi’an University of Technology, Xi’an 710082, China

Funds: The National Natural Science Foundation of China (61771388, 61801378), Xi’an Science and Technology Plan Project (201805037YD15CG21(11))

Received Date: 2018-07-24
Rev Recd Date: 2019-01-28

Available Online: 2019-02-15

Publish Date: 2019-06-01

Abstract

Abstract

A 10 bit fully differential dual slope Analog-to-Digital Converter (ADC) for Time Delay Integration (TDI) CMOS image sensors is realized based on column-parallel single-slope ADC. Top plates of the two capacitors are used for sampling differential inputs, and the bottom plates are connected to ramp generator for conversion. Current steering is used to generate the rising and falling ramp with the same step voltage simultaneously. The proposed ADC is fabricated in SMIC 0.18 μm CMOS process. Simulated spurious free dynamic range and effective number of bits are 87.92 dB and 9.84 bit with the input frequency of 1.32 kHz at 19.49 kS/s sampling rate, respectively. Measured results show that the ADC has a differential nonlinearity of –0.7/+0.6 LSB and integral nonlinearity of –2.6/+2.1 LSB.
- Column-parallel Analog-to-Digital Converter (ADC),
- Differential input,
- Current-steering ramp generator,
- Comparator

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References(17)

References

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