Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System

Xiaoqiang LIU; Guoshun YUAN; Shushan QIAO

doi:10.11999/JEIT180641

Volume 41 Issue 5

Apr. 2019

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Xiaoqiang LIU, Guoshun YUAN, Shushan QIAO. Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641

Citation:

Xiaoqiang LIU, Guoshun YUAN, Shushan QIAO. Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641

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Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System

doi: 10.11999/JEIT180641

1.
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China

Funds: The National Natural Science Foundation of China (61474135)

Received Date: 2018-07-02
Rev Recd Date: 2018-01-10

Available Online: 2019-01-22

Publish Date: 2019-05-01

Abstract

Abstract

In order to reduce the functional verification cycle of application-specific integrated circuits and on-chip system, a method for accelerating functional verification with FPGA digital hard processor system is proposed. The proposed method combines the advantages of software simulation function verification and field programmable gate array prototype verification, and uses the hard processor system integrated in the on-chip system field programmable gate array device as the verification excitation generation and the function verification coverage analysis unit. It solves the problem that verification speed and flexibility can not be unified. Compared with software simulation verification, the proposed method can effectively shorten the functional verification time of digital circuits; it is superior to existing FPGA prototyping technology in terms of functional verification efficiency and verification of intellectual property reusability.

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References(17)

References

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