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Volume 41 Issue 5
Apr.  2019
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Yingjian YAN, Min LIU, Zhaoyang QIU. Design and Implementation of Hardware Trojan Detection Algorithm for Coarse-grained Reconfigurable Arrays[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1257-1264. doi: 10.11999/JEIT180484
Citation: Yingjian YAN, Min LIU, Zhaoyang QIU. Design and Implementation of Hardware Trojan Detection Algorithm for Coarse-grained Reconfigurable Arrays[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1257-1264. doi: 10.11999/JEIT180484

Design and Implementation of Hardware Trojan Detection Algorithm for Coarse-grained Reconfigurable Arrays

doi: 10.11999/JEIT180484
  • Received Date: 2018-05-21
  • Rev Recd Date: 2018-09-20
  • Available Online: 2018-10-22
  • Publish Date: 2019-05-01
  • Hardware Trojan horse detection has become a hot research topic in the field of chip security. Most existing detection algorithms are oriented to ASIC circuits and FPGA circuits, and rely on golden chips that are not infected with hardware Trojan horses, which are difficult to adapt to the coarse-grained reconfigurable array consisting of large-scale reconfigurable cells. Therefore, aiming at the structural characteristics of Coarse-grained reconfigurable cryptographic logical arrays, a hardware Trojan horse detection algorithm based on partitioned and multiple variants logic fingerprints is proposed. The algorithm divides the circuit into multiple regions, adopts the logical fingerprint feature as the identifier of the region, and realizes the hardware Trojan detection and diagnosis without golden chip by comparing the multiple variant logic fingerprints of the regions in both dimensions of space and time. Experimental results show that the proposed detection algorithm has high detection success rate and low misjudgment rate for hardware Trojan detection.
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  • AGRAWAL D, BAKTIR S, KARAKOYUNLU D, et al. Trojan detection using IC fingerprinting[C]. IEEE Symposium on Security and Privacy. IEEE Computer Society, Berkeley, USA, 2007: 296–310.
    KITSOS P, SIMOS D E, TORRES-Jimenez J, et al. Exciting FPGA cryptographic trojans using combinatorial testing[C]. IEEE International Symposium on Software Reliability Engineering, Gaithersbury, USA, 2016: 69–76.
    赵剑锋, 史岗. 硬件木马研究动态综述[J]. 信息安全学报, 2017, 2(1): 74–90. doi: 10.19363/j.cnki.cn10-1380/tn.2017.01.006

    ZHAO Jianfeng and SHI Gang. A survey on the studies of hardware trojan[J]. Journal of Cyber Security, 2017, 2(1): 74–90. doi: 10.19363/j.cnki.cn10-1380/tn.2017.01.006
    COMPTON K and HAUCK S. Reconfigurable computing: A survey of systems and software[J]. ACM Computing Surveys, 2002, 34(2): 171–210. doi: 10.1145/508352.508353v
    VEERANNA N and SCHAFER B C. Hardware trojan avoidance and detection for dynamically re-configurable FPGAs[C]. International IEEE Conference on Field-Programmable Technology. Xi'an, China, 2017: 193–196.
    LIU Leibo, ZHOU Zhuoquan, WEI Shaojun, et al. DRMaSV: Enhanced capability against hardware trojans in coarse grained reconfigurable architectures[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 37(4): 782–795. doi: 10.1109/TCAD.2017.2729340
    KHALEGHI B, AHARI A, ASADI H, et al. FPGA-based protection scheme against hardware trojan horse insertion using dummy logic[J]. IEEE Embedded Systems Letters, 2015, 7(2): 46–50. doi: 10.1109/LES.2015.2406791
    PIRPILIDIS F, STEFANIDIS K G, VOYIATZIS A G, et al. On the effects of ring oscillator length and hardware Trojan size on an FPGA-based implementation of AES[J]. Microprocessors & Microsystems, 2017, 54(1): 75–82. doi: 10.1016/j.micpro.2017.09.001
    SARAN T, RANJANI R S, DEVI M N, et al. A region based fingerprinting for hardware Trojan detection and diagnosis[C]. International Conference on Signal Processing and Integrated Networks. Noida, India. 2017: 166–172.
    MAL-SARKAR S, KARAM R, NARASIMHAN S, et al. Design and validation for FPGA trust under hardware trojan attacks[J]. IEEE Transactions on Multi-Scale Computing Systems, 2017, 2(3): 186–198. doi: 10.1109/TMSCS.2016.2584052
    陈韬, 罗兴国, 李校南, 等. 一种基于流处理框架的可重构分簇式分组密码处理结构模型[J]. 电子与信息学报, 2014, 36(12): 3027–3034. doi: 10.3724/SP.J.1146.2014.00023

    CHEN Tao, LUO Xingguo, LI Xiaonan, et al. An architecture of stream based reconfigurable clustered block cipher processing array[J]. Journal of Electronics &Information Technology, 2014, 36(12): 3027–3034. doi: 10.3724/SP.J.1146.2014.00023
    WAKSMAN A and SETHUMADHAVAN S. Silencing hardware backdoors[C]. IEEE Security and Privacy. Berkeley, USA, 2011: 49–63.
    SASHANK K A, REDDY H S, PAVITHRAN P, et al. Hardware trojan detection using effective test patterns and selective segmentation[C]. International Symposium on Security in Computing and Communication. Singapore, 2017: 379–386.
    SALMANI H, TEHRANIPOOR M, and PLUSQUELLIC J. A layout-aware approach for improving localized switching to detect hardware trojans in integrated circuits[C]. IEEE International Workshop on Information Forensics and Security, Seattle, USA, 2011: 1–6.
    XIAO Kan, FORTE D, JIN Yier, et al. Hardware trojans: lessons learned after one decade of research[J]. ACM Transactions on Design Automation of Electronic Systems, 2016, 22(1): 1–23. doi: 10.1145/2906147
    MCINTYRE D, WOLFF F, PAPACHRISTOU C, et al. Trustworthy computing in a multi-core system using distributed scheduling[C]. IEEE On-Line Testing Symposium. Corfu, Greece, 2010: 211–213.
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