Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC

Zhenhai CHEN; Jinghe WEI; Hongwen QIAN; Zongguang YU; Xiaobo SU; Yan XUE; Hong ZHANG

doi:10.11999/JEIT180337

Volume 41 Issue 3

Mar. 2019

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Article Navigation > Journal of Electronics & Information Technology > 2019 > 41(3): 732-738

Zhenhai CHEN, Jinghe WEI, Hongwen QIAN, Zongguang YU, Xiaobo SU, Yan XUE, Hong ZHANG. Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC[J]. Journal of Electronics & Information Technology, 2019, 41(3): 732-738. doi: 10.11999/JEIT180337

Citation:

Zhenhai CHEN, Jinghe WEI, Hongwen QIAN, Zongguang YU, Xiaobo SU, Yan XUE, Hong ZHANG. Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC[J]. Journal of Electronics & Information Technology, 2019, 41(3): 732-738. doi: 10.11999/JEIT180337

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Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC

doi: 10.11999/JEIT180337

Zhenhai CHEN^{1, 2},
Jinghe WEI^{2
,
,},
Hongwen QIAN²,
Zongguang YU^{2, 3},
Xiaobo SU^{2, 3},
Yan XUE²,
Hong ZHANG⁴

1.
School of Information Engineering, Huangshan University, Huangshan 245041, China
2.
No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
3.
Microelectronic Institute, Xidian University, Xi’an 710071, China
4.
School of Microelectronic, Xi’an Jiaotong University, Xi’an 710049, China

Funds: The National Natural Science Foundation of China (61704161)

Received Date: 2018-04-21
Rev Recd Date: 2018-11-22

Available Online: 2018-12-05

Publish Date: 2019-03-01

Abstract

Abstract

A high precision common mode level insensitive sample and hold front-end circuit for charge domain pipelined Analog-to-Digital Converter (ADC) is proposed. The sample and hold circuit can be used to compensate the common mode charge errors caused by the variation of input common mode level in charge domain pipelined ADCs. Based on the proposed sample and hold circuit, a 14-bit 210 MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show the 14-bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dBc, with 30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm².
- Pipelined Analog-to-Digital Converter (ADC),
- Charge-domain,
- Sample and hold,
- Low power,
- Common-mode charge

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References(16)

References

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