High Throughput Dual-mode Reconfigurable Floating-point FFT Processor

Xing WEI; Zhihong HUANG; Haigang YANG

doi:10.11999/JEIT180170

Volume 40 Issue 12

Nov. 2018

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Article Navigation > Journal of Electronics & Information Technology > 2018 > 40(12): 3042-3050

Xing WEI, Zhihong HUANG, Haigang YANG. High Throughput Dual-mode Reconfigurable Floating-point FFT Processor[J]. Journal of Electronics & Information Technology, 2018, 40(12): 3042-3050. doi: 10.11999/JEIT180170

Citation:

Xing WEI, Zhihong HUANG, Haigang YANG. High Throughput Dual-mode Reconfigurable Floating-point FFT Processor[J]. Journal of Electronics & Information Technology, 2018, 40(12): 3042-3050. doi: 10.11999/JEIT180170

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High Throughput Dual-mode Reconfigurable Floating-point FFT Processor

doi: 10.11999/JEIT180170

Xing WEI^{1, 2},
Zhihong HUANG¹,
Haigang YANG^{1, 2
,
,}

1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100190, China

Funds: The National Natural Science Foundation of China (61704173, 61474120), The Major Program of Beijing Science and Technology (Z171100000117019)

Received Date: 2018-02-08
Rev Recd Date: 2018-07-05

Available Online: 2018-07-24

Publish Date: 2018-12-01

Abstract

Abstract

In the advanced applications of real-time radar imaging and high-precision scientific computing systems, the design of high throughput and reconfigurable Floating-Point (FP) FFT accelerator is significant. Achieving high throughput FP FFT with low area and power cost poses a greater challenge due to high complexity of FP operations in comparison to fixed-point implementations. To address these issues, a serial of mixed-radix algorithms for 128/256/512/1024/2048-point FFT are proposed by decomposing long FFT into short implementations with cascaded radix-2^k stages so that the complexity of multiplications can be significantly reduced. Besides, two novel fused FP add-subtract and dot-product units for dual-mode functionality are proposed, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. Thus, a high throughput dual-mode floating-point variable length FFT is designed. The proposed processor is implemented based on SMIC 28 nm CMOS technology. Simulation results show that the throughput and Signal-to-Quantization Noise Ratio (SQNR) in single-channel single precision and dual-channel half precision floating-point mode are 3.478 GSample/s, 135 dB and 6.957 GSample/s, 60 dB respectively. Compare to the other FP FFT, this processor can achieve 12 times improvement of normalized throughput-area ratio.
- Fast Fourier Transform (FFT),
- Dual-mode floating point,
- Mixed-radix,
- Fused arithmetic unit

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